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tm data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7234 features ? fully integrated 1553a/b notice 2, mcair, stanag 3838 interface terminal compatible with mini-ace (plus) and ace generations choice of : - rt or bc/rt/mt in same footprint - rt or bc/rt/mt with 4k ram - bc/rt/mt with 64k ram, and ram parity choice of 5v or 3.3v logic 5v transceiver with 1760 and mcair compatible options comprehensive built-in self-test flexible processor/memory interface, with reduced host wait time choice of 10, 12, 16, or 20 mhz clock highly autonomous bc with built-in message sequence control: - frame scheduling - branching - asynchronous message insertion - general purpose queue - user-defined interrupts advanced rt functions - global circular buffering - interrupt status queue - 50% circular buffer rollover interrupts selective message monitor - selection by address, t/r bit, subaddress - command and data stacks - 50% and 100% stack rollover interrupts description the enhanced miniature advanced communications engine (enhanced mini-ace) family of mil-std-1553 terminals provide com- plete interfaces between a host processor and a 1553 bus, and integrate dual transceiver, protocol logic, and 4k words or 64k words of ram. these terminals are nearly 100% footprint and software compatible with the previous generation mini-ace (plus) terminals, and are soft- ware compatible with the older ace series. they are powered by a choice of 5v or 3.3v logic. multiprotocol sup- port of mil-std-1553a/b and stanag 3838, including versions incorporating mcair compatible transmitters, is provided. there is a choice of 10, 12, 16, or 20 mhz clocks. the bc/rt/mt versions with 64k words of ram include built-in ram parity checking. bc features include a built-in message sequence control engine, with a set of 20 instructions. this provides an autonomous means of implementing multi-frame message scheduling, message retry schemes, data double buffering, asynchronous message insertion, and reporting to the host cpu. the enhanced mini-ace incorporates a fully autonomous built-in self-test, which provides comprehensive testing of the internal protocol logic and/or ram. the rt offers the same choices of subaddress buffering as the ace and mini-ace (plus), along with a global circular buffering option, 50% rollover interrupt for circular buffers, an interrupt status queue, and an "auto-boot" option to support mil-std-1760. these terminals provide the same flexibility in host interface configu- rations as the ace/mini-ace, along with a reduction in the host processor's worst case holdoff time. ? 2000 data device corporation bu-6174x/6184x/6186x enhanced miniature advanced communications engine make sure the next card you purchase has...
2 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c figure 1. enhanced mini-ace block diagram transceiver a ch. a transceiver b ch. b dual encoder/decoder, multiprotocol and memory management rt address shared ram address bus processor and memory interface logic data bus d15-d0 a15-a0 data buffers address buffers processor data bus processor address bus miscellaneous incmd/mcrst clk_in, mstclr,ssflag/ext_trg, tx-inh_a, tx-inh_b, upaddren rtad4-rtad0, rtadp transparent/buffered, strbd, select, rd/wr, mem/reg, trigger_sel/memena-in, msb/lsb/dtgrt ioen, readyd addr_lat/memoe, zero_wait/memwr, 8/16-bit/dtreq, polarity_sel/dtack int processor and memory control interrupt request tx/rx_a tx/rx_a tx/rx_b tx/rx_b * * see ordering information for available memory
3 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c v v v ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma 5.5 3.6 5.25 180 285 390 600 180 296 412 645 120 225 330 540 40 120 236 352 585 40 160 265 370 580 160 276 392 625 100 205 310 520 40 100 216 332 565 40 4.5 3.0 4.75 power supply requirements voltages/tolerances ! +5v (ram for 61864(5), logic for bu-61xx5) (note 12) ! +3.3v (logic for bu-61xx3/4) (note 12) ! +5v (ch. a, ch. b) current drain (total hybrid) ! bu-61865xx-xx0 +5v (logic, ram, ch. a, ch. b) ? idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61865x3-xx2 +5v (logic, ram, ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61864xx-xx0 +5v (ram, ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle 3.3v logic ! bu-61864x3-xx2 +5v (ram, ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle 3.3v logic ! bu-61745xx-xx0. bu-61845xx-xx0 +5v (logic, ram, ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61745x3-xx2. bu-61845x3-xx2 +5v (logic, ram, ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61743xx-xx0, bu-61843xx-xx0 +5v (ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle 3.3v logic ! bu-61743x3-xx2, bu-61843x3-xx2 +5v (ch. a, ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle 3.3v logic units max typ min parameter table 1. enhanced mini-ace series specifications (cont.) 5.0 3.3 5.0 v v v v v v a a a a a a a a v v v v ma ma pf pf 0.7 0.2vcc 10 -50 10 -33 -50 -33 10 10 0.4 0.4 -3.4 50 50 2.1 0.8vcc 0.4 1.0 -10 -350 -10 -350 -350 -350 -10 -10 2.4 2.4 3.4 logic v ih all signals except clk_in clk_in v il all signals except clk_in clk_in schmidt hysteresis all signals except clk_in clk_in i ih, i il all signals except clk_in i ih (vcc=5.25v, v in =vcc) i ih (vcc=5.25v, v in =2.7v) i ih (vcc=3.6v, v in =vcc) i ih (vcc=3.6v, v in =2.7v) i il (vcc=5.25v, v in =0.4v) i il (vcc=3.6v, v in =0.4v) clk_in i ih i il v oh (vcc=4.5v, v ih =2.7v, v il =0.2v, i oh =max) v oh (vcc=3.0v, v ih =2.7v, v il =0.2v, i oh =max) v ol (vcc=4.5v, v ih =2.7v, v il =0.2v, i ol =max) v ol (vcc=3.0v, v ih =2.7v, v il =0.2v, i ol =max) i ol i oh c i (input capacitance) c io (bi-directional signal input capacitance) vp-p vp-p vp-p mvp-p mv p nsec nsec 9 27 27 10 250 300 300 7 20 22 150 250 6 18 20 -250 100 200 transmitter differential output voltage ! direct coupled across 35 ? , measured on bus ! transformer coupled across 70 ? , measured on bus (bu-61xxxxx-xx0, bu-61xxxxx-xx2) (note 13) output noise, differential (direct coupled) output offset voltage, transformer coupled across 70 ohms rise/fall time (bu-61xxxx3, bu-61xxxx4) k ? pf vp-p vpeak 5 0.860 10 2.5 0.200 receiver differential input resistance (notes 1-6) differential input capacitance (notes 1-6) threshold voltage, transformer coupled, measured on stub common mode voltage (note 7) v v v v v 6.0 6.0 7.0 6.0 6.0 -0.3 -0.3 -0.3 -0.3 -0.3 absolute maximum rating supply voltage ! logic +5v or +3.3v ! ram +5v ! transceiver +5v (note 12) logic ! voltage input range for +5v logic (bu-61xx5) ! voltage input range for +3.3v logic (bu-61xx3/4) units max typ min parameter table 1. enhanced mini-ace series specifications
4 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c in. (mm) 1.0 x 1.0 x 0.155 (25.4 x 25.4 x 3.94) c c c c/w c c c c s s s s s s s s s % % % +125 +85 +70 11 125 160 150 +300 19.5 23.5 51.5 131 7 0.001 0.01 60 9 2.5 9.5 10.0 to 10.5 18. 22.5 50.5 129.5 660.5 -55 -40 0 -55 -65 17.5 21.5 49.5 127 4 -0.001 -0.01 40 weight flatpack/gull lead package oz (g) 0.6 (17) physical characteristics size flatpack/gull lead package thermal ! operating case/ball temperature -1xx, -4xx -2xx, -5xx -3xx, -8xx ! ceramic flatpack / gull lead thermal resistance, junction-to-case, hottest die ( jc ) max case temperature operating junction temperature storage temperature lead temperature (soldering, 10 sec.) 1553 message timing completion of cpu write (bc start)-to-start of next message for (non-enhanced bc mode) bc intermessage gap (note 8) non-enhanced (mini-ace compatible) bc mode enhanced bc mode (note 9) bc/rt/mt response timeout (note 10) ! 18.5 nominal ! 22.5 nominal ! 50.5 nominal ! 128.0 nominal rt response time (mid-parity to mid-sync) (note 11) transmitter watchdog timeout clock input (cont) ! short term tolerance, 1 second 1553a compliance 1553b compliance ! duty cycle units max typ min parameter table 1. enhanced mini-ace series specifications (cont.) w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w 0.99 1.22 1.45 1.90 0.99 1.28 1.58 2.16 0.80 1.03 1.26 1.71 0.80 1.09 1.39 1.97 0.88 1.11 1.33 1.79 0.88 1.17 1.46 2.05 0.69 0.92 1.15 1.60 0.69 0.98 1.28 1.86 0.28 0.51 0.75 1.22 0.28 0.58 0.88 1.48 power dissipation (note 14) total hybrid ! bu-61865xx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61865x3-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61864xx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61864x3-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61745xx-xx0, bu-61845xx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61745x3-xx2, bu-61845x3-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61743xx-xx0, bu-61843xx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61743x3-xx2, bu-61843x3-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle hottest die ! bu-61xxxxx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle ! bu-61xxxx3-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle units max typ min parameter table 1. enhanced mini-ace series specifications (cont.) mhz mhz mhz mhz % % 0.01 0.1 -0.01 -0.10 clock input frequency ! nominal value default mode option option option ! long term tolerance 1553a compliance 1553b compliance 16.0 12.0 10.0 20.0 table 1 notes: notes 1 through 6 are applicable to the receiver differential resistance and differential capacitance specifications: (1) specifications include both transmitter and receiver (tied together internally).
5 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c introduction the bu-61740/61743/61745 rt, and bu-61840/61843/61845/ 61860/61864/61865 bc/rt/mt enhanced mini-ace family of mil-std-1553 terminals comprise a complete integrated inter- face between a host processor and a mil-std-1553 bus. all members of the enhanced mini-ace family are packaged in the same 1.0 square inch flatpack package. the enhanced mini- ace hybrids are nearly 100% footprint and software compatible with the previous generation mini-ace and mini-ace plus termi- nals, and are software compatible with the original ace series. the enhanced mini-ace provides complete multiprotocol sup- port of mil-std-1553a/b/mcair and stanag 3838. all versions integrate dual transceiver; along with protocol, host interface, memory management logic; and a minimum of 4k words of ram. in addition, the bu-61864 and bu-61865 bc/rt/mt ter- minals include 64k words of internal ram, with built-in parity checking. the enhanced mini-aces include a 5v, voltage source trans- ceiver for improved line driving capability, with options for mil- std-1760 and mcair compatibility. as a means of reducing power consumption, there are versions for which the logic is powered by 3.3v, rather than 5v. to provide further flexibility, the enhanced mini-ace may operate with a choice of 10, 12, 16, or 20 mhz clock inputs. one of the new salient features of the enhanced mini-ace is its enhanced bus controller architecture. the enhanced bc's high- ly autonomous message sequence control engine provides a means for offloading the host processor for implementing multi- frame message scheduling, message retry schemes, data dou- ble buffering, and asynchronous message insertion. for the pur- pose of performing messaging to the host processor, the enhanced bc mode includes a general purpose queue, along with user-defined interrupts. a second major new feature of the enhanced mini-ace is the incorporation of a fully autonomous built-in self-test. this test provides comprehensive testing of the internal protocol logic. a separate test verifies the operation of the internal ram. since the self-tests are fully autonomous, they eliminate the need for the host to write and read stimulus and response vectors. the enhanced mini-ace rt offers the same choices of single, double, and circular buffering for individual subaddresses as ace and mini-ace (plus). new enhancements to the rt archi- tecture include a global circular buffering option for multiple (or all) receive subaddresses, a 50% rollover interrupt for circular buffers, an interrupt status queue for logging up to 32 interrupt events, and an option to automatically initialize to rt mode with the busy bit set. the interrupt status queue and 50% rollover interrupt features are also included as improvements to the enhanced mini-ace's monitor architecture. to minimize board space and "glue" logic, the enhanced mini- ace terminals provide the same wide choice of host interface configurations as the ace and mini-ace (plus). this includes support of interfaces to 16-bit or 8-bit processors, memory or port type interfaces, and multiplexed or non-multiplexed (2) impedance parameters are specified directly between pins tx/rx_a(b) and tx/rx_a(b) of the enhanced mini-ace hybrid. (3) it is assumed that all power and ground inputs to the hybrid are con- nected. (4) the specifications are applicable for both unpowered and powered conditions. (5) the specifications assume a 2 volt rms balanced, differential, sinu- soidal input. the applicable frequency range is 75 khz to 1 mhz. (6) minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. (7) assumes a common mode voltage within the frequency range of dc to 2 mhz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), and referenced to hybrid ground. transformer must be a ddc recommended transformer or other transformer that provides an equivalent minimum cmrr. (8) typical value for minimum intermessage gap time. under software control, this may be lengthened to 65,535 ms - message time, in increments of 1 s. if enhanced cpu access, bit 14 of configuration register #6, is set to logic "1", then host accesses during bc start-of-message (som) and end-of-message (eom) transfer sequences could have the effect of lengthening the inter- message gap time. for each host access during an som or eom sequence, the intermessage gap time will be lengthened by 6 clock cycles. since there are 7 internal transfers during som, and 5 dur- ing eom, this could theoretically lengthen the intermessage gap by up to 72 clock cycles; i.e., up to 7.2 ms with a 10 mhz clock, 6.0 s with a 12 mhz clock, 4.5 s with a 16 mhz clock, or 3.6 s with a 20 mhz clock. (9) for enhanced bc mode, the typical value for intermessage gap time is approximately 10 clock cycles longer than for the non- enhanced bc mode. that is, an addition of 1.0 s at 10 mhz, 833 ns at 12 mhz, 625 ns at 16 mhz, or 500 ns at 20 mhz. (10) software programmable (4 options). includes rt-to-rt timeout (measured mid-parity of transmit command word to mid-sync of transmitting rt status word). (11) measured from mid-parity crossing of command word to mid-sync crossing of rt's status word. (12) external 10 f tantalum and 0.1 f capacitors should be located as close as possible to pins 20 and 72, and a 0.1 f at pin 37. for bu-61864 and bu-61865, there should also be a 0.1 f at pin 26. (13) mil-std-1760 requires a 20 vp-p minimum output on the stub connection. (14) power dissipation specifications assume a transformer coupled configuration with external dissipation (while transmitting) of: 0.14 watts for the active isolation transformer, 0.08 watts for the active bus coupling transformer, 0.45 watts for each of the two bus isolation resistors and 0.15 watts for each of the two bus termination resistors. notes: (cont?d)
6 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c address/data buses. in addition, with respect to ace/mini-ace (plus), the worst case processor wait time has been significant- ly reduced. for example, assuming a 16 mhz clock, this time has been reduced from 2.8 s to 632 ns for read accesses, and to 570 ns for write accesses. the enhanced mini-ace series terminals operate over the full military temperature range of -55 to +125c. available screened to mil-prf-38534c, the terminals are ideal for military and industrial processor-to-1553 applications. transceivers the transceivers in the enhanced mini-ace series terminals are fully monolithic, requiring only a +5 volt power input. the trans- mitters are voltage sources, which provide improved line driving capability over current sources. this serves to improve perfor- mance on long buses with many taps. the transmitters also offer an option which satisfies the mil-std-1760 requirement for a minimum of 20 volts peak-to-peak, transformer coupled output. besides eliminating the demand for an additional power supply, the use of a +5v only transceiver requires the use of a step-up, rather than a step-down, isolation transformer. this provides the advantage of a higher terminal input impedance than is possible for a 15 volt or 12 volt transmitter. as a result, there is a greater margin for the input impedance test, mandated for the 1553 val- idation test. this characteristic allows for longer cable lengths between a system connector and the isolation transformers of an embedded 1553 terminal. to provide compatibility to mcair specs, the enhanced mini- aces are available with an option for transmitters with increased rise and fall times. additionally, for mil-std-1760 applications, the enhanced mini- ace provides an option for a minimum stub voltage level of 20 volts peak-to-peak, transformer coupled. the receiver sections of the enhanced mini-ace are fully compli- ant with mil-std-1553b notice 2 in terms of front end overvoltage protection, threshold, common mode rejection, and word error rate. register and memory addressing the software interface of the enhanced mini-ace to the host processor consists of 24 internal operational registers for normal operation, an additional 24 test registers, plus 64k words of shared memory address space. the enhanced mini-ace's 4k x 16 or 64k x 17 internal ram resides in this address space. for normal operation, the host processor only needs to access the lower 32 register address locations (00-1f). the next 32 locations (20-3f) should be reserved, since many of these are used for factory test. internal registers the address mapping for the enhanced mini-ace registers is illustrated in table 2. bc general purpose queue pointer / rt-mt interrupt status queue pointer register (rd/wr) 1 1 1 1 1 bc general purpose flag register (wr) interrupt mask register #2 (rd/wr) reserved 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 interrupt status register #2 (rd) bc condition code register (rd) bit test status register (rd) configuration register #7 (rd/wr) 0 1 0 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 configuration register #6 (rd/wr) 0 0 0 1 1 test mode register 7 1 1 1 0 1 test mode register 6 test mode register 4 test mode register 2 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 test mode register 5 test mode register 3 test mode register 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 1 test mode register 0 0 0 0 0 1 rt bit word register (rd) 1 1 1 1 0 rt status word register (rd) 0 1 1 1 0 non-enhanced bc frame time / enhanced bc initial instruction pointer / rt last command / mt trigger word register(rd/wr) 1 0 1 1 0 bc time remaining to next message register (rd) 0 0 1 1 0 bc frame time remaining register (rd) 1 1 0 1 0 rt / monitor data stack address register (rd) 0 1 0 1 0 configuration register #5 (rd/wr) 1 0 0 1 0 configuration register #4 (rd/wr) 0 0 0 1 0 configuration register #3 (rd/wr) 1 1 1 0 0 interrupt status register #1 (rd) 0 1 1 0 0 time tag register (rd/wr) 1 0 1 0 0 bc control word / rt subaddress control word register (rd/wr) 0 0 1 0 0 non-enhanced bc/rt command stack pointer / enhanced bc instruction list pointer register (rd) 1 1 0 0 0 start/reset register (wr) 1 1 0 0 0 configuration register #2 (rd/wr) 0 1 0 0 0 configuration register #1 (rd/wr) 1 0 0 0 0 interrupt mask register #1 (rd/wr) 0 0 0 0 0 a0 a1 a2 a3 a4 register description/accessibility address lines table 2. address mapping
7 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c table 3. interrupt mask register #1 (read/write 00h) bit description 15(msb) reserved 14 ram parity error 13 bc/rt transmitter timeout 12 bc/rt command stack rollover 11 mt command stack rollover 10 mt data stack rollover 9 handshake fail 8 bc retry 7 rt address parity error 6 time tag rollover 5 rt circular buffer rollover 4 bc control word/rt subaddress control word eom 3 bc end of frame 2 format error 1 bc status set/rt mode code/mt pattern trigger 0(lsb) end of message table 4. configuration register #1 (read/write 01h) bit bc function (bits 11-0 enhanced mode only) rt without alternate status rt with alternate status (enhanced only) monitor function (enhanced mode only bits 12-0) 15 (msb) rt/bc-mt (logic 0) (logic 1) (logic 1) (logic 0) 14 mt/bc-r t (logic 0) (logic 0) (logic 0) (logic 1) 13 current area b/a current area b/a current area b/a current area b/a 12 message stop-on-error message monitor enabled (mmt) message monitor enabled message monitor enabled 11 frame stop-on-error s10 trigger word enabled 10 status set stop-on-message b usy s09 start-on-trigger 9 status set stop-on-frame ser vice req uest s08 stop-on-trigger 8 frame auto-repeat ssfla g s07 not used 7 external trigger enabled r tfla g (enhanced mode only) s06 external trigger enabled 6 internal trigger enabled not used s05 not used 5 intermessage gap timer enabled not used s04 not used 4 retry enabled not used s03 not used 3 doubled/single retry not used s02 not used 2 bc enabled (read only) not used s01 monitor enabled(read only) 1 bc frame in progress (read only) not used s00 monitor triggered (read only) 0 (lsb) bc message in progress (read only) rt message in progress (enhanced mode only,read only) rt message in progress (read only) monitor active (read only) d ynamic b us contr ol a ccept ance
8 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c separate broadcast data 0(lsb) enhanced rt memory management 1 clear service request 2 level/pulse interrupt request 3 interrupt status auto clear 4 load time tag on synchronize 5 clear time tag on synchronize 6 time tag resolution 0 7 time tag resolution 1 8 time tag resolution 2 9 256-word boundary disable 10 overwrite invalid data 11 rx sa double buffer enable 12 busy lookup table enable 13 ram parity enable 14 enhanced interrupts 15(msb) description bit table 5. configuration register #2 (read/write 02h) table 6. start/reset register (write 03h) bit description 15(msb) reserved 14 reserved 12 13 reserved reserved 8 10 9 11 reserved clear self-test register initiate ram self-test clear rt halt 7 initiate protocol self-test 6 bc/mt stop-on-message 5 bc stop-on-frame 4 time tag test clock 3 time tag reset 2 interrupt reset 1 bc/mt start 0(lsb) reset command stack pointer 0 0(lsb) ? ? ? ? ? ? command stack pointer 15 15(msb) description bit table 7. bc/rt command stack pointer reg. (read 03h) rt-to-rt format 0(lsb) broadcast format 1 mode code format 2 subsystem flag bit mask 1553a/b select 3 eom interrupt enable 4 mask broadcast bit 5 off-line self-test 6 bus channel a/b 7 retry enabled 8 reserved bits mask 9 terminal flag bit mask 10 busy bit mask 12 service request bit mask 13 message error mask 14 transmit time tag for synchronize mode com- mand 15(msb) description bit 11 table 8. bc control word register (read/write 04h) bcst: memory management 0 (mm0) 0(lsb) bcst: memory management 1 (mm1) 1 bcst:memory management 2 (mm2) 2 tx: memory management 1 (mm1) bcst: circ buf int 3 bcst: eom int 4 rx: memory management 0 (mm0) 5 rx: memory management 1 (mm1) 6 rx: memory management 2 (mm2) 7 rx: circ buf int 8 rx: eom int 9 tx: memory management 0 (mm0) 10 tx: memory management 2 (mm2) 12 tx: circ buf int 13 tx: eom int 14 rx: double buffer enable 15(msb) description bit 11 table 9. rt subaddress control word (read/write 04h) time tag 0 0(lsb) ? ? ? ? ? ? time tag 15 15(msb) description bit table 10. time tag register (read/write 05h)
9 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c end of message 0(lsb) bc status set / rt mode code / mt pattern trigger 1 format error 2 mt command stack rollover bc end of frame 3 bc control word/rt subaddress control word eom 4 rt circular buffer rollover 5 time tag rollover 6 rt address parity error 7 bc retry 8 handshake fail 9 mt data stack rollover 10 bc/rt command stack rollover 12 transmitter timeout 13 ram parity error 14 master interrupt 15(msb) description bit 11 table 11. interrupt status register #1 (read 06h) enhanced mode code handling 0(lsb) 1553a mode codes enable 1 r tf ail / r tfla g wrap enable 2 mt command stack size 0 busy rx transfer disable 3 illegal rx transfer disable 4 alternate status word enable 5 override mode t/r error 6 illegalization disabled 7 mt data stack size 0 8 mt data stack size 1 9 mt data stack size 2 10 mt command stack size 1 12 bc/rt command stack size 0 13 bc/rt command stack size 1 14 enhanced mode enable 15(msb) description bit 11 table 12. configuration register #3 (read/write 07h) rt address parity 0(lsb) rt address 0 1 rt address 1 2 expanded crossing enabled rt address 2 3 rt address 3 4 rt address 4 5 rt address latch/transp arent 6 broadcast disabled 7 gap check enabled 8 response timeout select 0 9 response timeout select 1 10 external tx inhibit b 12 external tx inhibit a 13 single-ended select 14 12 / 16 mhz clock select 15(msb) description bit 11 table 14. configuration register #5 (read/write 09h) rt / monitor data stack address 0 0(lsb) ? ? ? ? ? ? rt / monitor data stack address 15 15(msb) description bit table 15. rt / monitor data stack address register (read/write 0ah) test mode 0 0(lsb) test mode 1 1 test mode 2 2 broadcast mask ena/xor latch rt address with config #5 3 mt tag gap option 4 valid busy/no data 5 valid m.e./no data 6 2nd retry alt/same bus 7 1st retry alt/same bus 8 retry if status set 9 retry if -a and m.e. 10 expanded bc control word enable 12 mode command override busy 13 inhibit bit word if busy 14 external bit word enable 15(msb) description bit 11 table 13. configuration register #4 (read/write 08h)
10 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c bc frame time remaining 0 0(lsb) ? ? ? ? ? ? bc frame time remaining 15 15(msb) description bit table 16. bc frame time remaining register (read/write 0bh) note: resolution = 100 s per lsb bc message time remaining 0 0(lsb) ? ? ? ? ? ? bc message time remaining 15 15(msb) description bit table 17. bc message time remaining register (read/write 0ch) note: resolution = 1 s per lsb bit 0 0(lsb) ? ? ? ? ? ? bit 15 15(msb) description bit table 18. bc frame time / rt last command / mt trigger register (read/write 0dh) table 19. rt status word register (read/write 0eh) 11 bit description 15(msb) logic ?0? 12 logic ?0? 14 logic ?0? 13 logic ?0? 10 message error 9 instrumentation 8 service request 7 reserved 6 reserved 5 reserved 4 broadcast command received 3 busy logic ?0? 2 ssflag 1 dynamic bus control accept 0(lsb) terminal flag command word contents error 0(lsb) rt-to-rt 2nd command word error 1 rt-to-rt no response error 2 transmitter shutdown b rt-to-rt gap / synch / address error 3 parity / manchester error received 4 incorrect sync received 5 low word count 6 high word count 7 bit test fail 8 terminal flag inhibited 9 transmitter shutdown a 10 handshake failure 12 loop test failure a 13 loop test failure b 14 transmitter timeout 15(msb) description bit 11 table 20. rt bit word register (read 0fh) clock select 0 0(lsb) clock select 1 1 64-word register space 2 global circular buffer size 2 reserved 3 enhanced message monitor 4 rt address source 5 interrupt status queue enable 6 disable valid messages to interrupt status queue 7 disable invalid messages to interrupt status queue 8 global circular buffer size 0 9 global circular buffer size 1 10 global circular buffer enable 12 command stack pointer increment on eom (rt, mt) 13 enhanced cpu access 14 enhanced bus controller 15(msb) description bit 11 table 21. configuration register #6 (read/write 18h)
11 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c mode code reset / incmd select 0(lsb) enhanced bc watchdog timer enabled 1 enhanced timetag synchronize 2 memory management base address 11 1553b response time 3 rt halt enable 4 reserved 5 reserved 6 reserved 7 reserved 8 reserved 9 memory management base address 10 10 memory management base address 12 12 memory management base address 13 13 memory management base address 14 14 memory management base address 15 15(msb) description bit 11 table 22. configuration register #7 (read/write 19h) less than flag / general purpose flag 1 0(lsb) equal flag / general purpose flag 1 1 general purpose flag 2 2 message status set general purpose flag 3 3 general purpose flag 4 4 general purpose flag 5 5 general purpose flag 6 6 general purpose flag 7 7 no response 8 format error 9 good block transfer 10 bad message 12 retry 0 13 retry 1 14 always 15(msb) description bit 11 table 23. bc condition register (read 1bh) set general purpose flag 0 0(lsb) set general purpose flag 1 1 set general purpose flag 2 2 clear general purpose flag 3 set general purpose flag 3 3 set general purpose flag 4 4 set general purpose flag 5 5 set general purpose flag 6 6 set general purpose flag 7 7 clear general purpose flag 0 8 clear general purpose flag 1 9 clear general purpose flag 2 10 clear general purpose flag 4 12 clear general purpose flag 5 13 clear general purpose flag 6 14 clear general purpose flag 7 15(msb) description bit 11 table 24. bc general purpose flag register (write 1bh) logic ?0? 0(lsb) logic ?0? 1 logic ?0? 2 protocol built-in-test complete / in-progress logic ?0? 3 logic ?0? 4 ram built-in test in-passed 5 ram built-in test in-progress 6 ram built-in test complete 7 logic ?0? 8 logic ?0? 9 logic ?0? 10 protocol built-in test abort 12 protocol built-in test passed 13 protocol built-in test in-progress 14 protocol built-in test complete 15(msb) description bit 11 table 25. bit test status flag register (read 1ch)
12 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c not used 0(lsb) bit test complete 1 enhanced bc irq0 2 call stack pointer register error enhanced bc irq1 3 enhanced bc irq2 4 enhanced bc irq3 5 monitor data stack 50% rollover 6 monitor command stack 50% rollover 7 rt circular buffer 50% rollover 8 rt command stack 50% rollover 9 bc trap op code 10 general purpose queue / interrupt status queue rollover 12 rt illegal command/message mt message received 13 bc op code parity error 14 not used 15(msb) description bit 11 table 26. interrupt mask register #2 (read/write 1dh) interrupt chain bit 0(lsb) bit test complete 1 enhanced bc irq0 2 call stack pointer register error enhanced bc irq1 3 enhanced bc irq2 4 enhanced bc irq3 5 monitor data stack 50% rollover 6 monitor command stack 50% rollover 7 rt circular buffer 50% rollover 8 rt command stack 50% rollover 9 bc trap op code 10 general purpose queue / interrupt status queue rollover 12 rt illegal command/message mt message received 13 bc op code parity error 14 master interrupt 15(msb) description bit 11 table 27. interrupt status register #2 (read 1eh) queue pointer address 0 0(lsb) queue pointer address 1 1 queue pointer address 2 2 queue pointer base address 11 queue pointer address 3 3 queue pointer address 4 4 queue pointer address 5 5 queue pointer base address 6 6 queue pointer base address 7 7 queue pointer base address 8 8 queue pointer base address 9 9 queue pointer base address 10 10 queue pointer base address 12 12 queue pointer base address 13 13 queue pointer base address 14 14 queue pointer base address 15 15(msb) description bit 11 table 28. bc general purpose queue pointer register rt, mt interrupt status queue pointer register (read/write1fh)
13 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c command word contents error 0(lsb) rt-to-rt 2nd command error 1 rt-to-rt gap / sync / address error 2 rt-to-rt format invalid word 3 incorrect data sync 4 word count error 5 illegal command word 6 data stack rollover 7 loop test fail 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15(msb) description bit 11 table 30. rt mode block status word gap time (lsb) mode_code 0(lsb) contiguous data / gap 1 channel b/a 2 command / d a t a 3 error 4 br o adcast 5 this r t 6 word flag 7 ? ? ? ? ? ? gap time (msb) 15(msb) description bit 8 table 32. word monitor identification word data word count / mode code bit 0 0(lsb) data word count / mode code bit 1 1 data word count / mode code bit 2 2 remote terminal address bit 0 data word count / mode code bit 3 3 data word count / mode code bit 4 4 subaddress / mode bit 0 5 subaddress / mode bit 1 6 subaddress / mode bit 2 7 subaddress / mode bit 3 8 subaddress / mode bit 4 9 transmit / receive 10 remote terminal address bit 1 12 remote terminal address bit 2 13 remote terminal address bit 3 14 remote terminal address bit 4 15(msb) description bit 11 table 31. 1553 command word note: tables 29 to 35 are not registers, but they are words stored in ram. invalid word 0(lsb) incorrect sync type 1 word count error 2 status set wrong status address / no gap 3 good data block transfer 4 retry count 0 5 retry count 1 6 masked status set 7 loop test fail 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15(msb) description bit 11 table 29. bc mode block status word
14 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c command word contents error 0(lsb) rt-to-rt 2nd command error 1 rt-to-rt gap / sync / address error 2 rt-to-rt transfer invalid word 3 incorrect sync 4 word count error 5 reserved 6 data stack rollover 7 good data block transfer 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15(msb) description bit 11 table 33. message monitor mode block status word terminal flag 0(lsb) dynamic bus control acceptance 1 ssflag 2 remote terminal address bit 0 busy 3 broadcast command received 4 reserved 5 reserved 6 reserved 7 service request 8 instrumentation 9 message error 10 remote terminal address bit 1 12 remote terminal address bit 2 13 remote terminal address bit 3 14 remote terminal address bit 4 15(msb) description bit 11 table 35. 1553b status word non-test register function summary a summary of the enhanced mini-ace's 24 non-test registers follows. interrupt mask registers #1 and #2 are used to enable and disable interrupt requests for various events and conditions. configuration registers #1 and #2 are used to select the enhanced mini-ace's mode of operation, and for software con- trol of rt status word bits, active memory area, bc stop-on- error, rt memory management mode selection, and control of the time tag operation. start/reset register is used for "command" type functions such as software reset, bc/mt start, interrupt reset, time tag reset, time tag register test, initiate protocol self-test, initiate ram self-test, clear self-test register, and clear rt halt. the start/reset register also includes provisions for stopping the bc in its auto-repeat mode, either at the end of the current message or at the end of the current bc frame. bc/rt command stack register allows the host cpu to deter- mine the pointer location for the current or most recent message. bc instruction list pointer register may be read to determine the current location of the instruction list pointer for the enhanced bc mode. bc control word/rt subaddress control word register: in bc mode, allows host access to the current word or most recent bc control word. the bc control word contains bits that select the active bus and message format, enable off-line self-test, ?1? for message interrupt event ?0? for non-message interrupt event 0 end-of-message (eom) ram parity error 1 subaddress control word eom protocol self-test complete 2 rt circular buffer 50% rollover not used mode code interrupt rt address parity error 3 format error time tag rollover 4 handshake fail not used 5 rt command (descriptor) stack rollover not used 6 rt command (descriptor) stack 50% rollover not used 7 monitor command (descriptor) stack rollover not used 8 monitor command (descriptor) stack 50% rollover not used 9 rt circular buffer rollover not used 10 monitor data stack rollover not used 12 monitor data stack 50% rollover not used 13 illegal command not used 14 transmitter timeout not used 15 definition for message interrupt event definition for non-message interrupt event bit 11 table 34. rt/monitor interrupt status word (for interrupt status queue)
15 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c bc frame time/ rt last command /mt trigger word register. in bc mode, this register is used to program the bc frame time, for use in the frame auto-repeat mode. the resolution of this reg- ister is 100 s/ls, with a range up to 6.55 seconds. in rt mode, this register stores the current (or most previous) 1553 command word processed by the enhanced mini-ace rt. in the word monitor mode, this register is used to specify a 16-bit trigger (command) word. the trigger word may be used to start or stop the monitor, or to generate interrupts. bc initial instruction list pointer register enables the host to assign the starting address for the enhanced bc instruction list. rt status word register and bit word registers provide read-only indications of the rt status and bit words. test mode registers 0-7 are included for factory test. in normal operation, these registers do not need to be accessed by the host processor. configuration registers #6 and #7 are used to enable the enhanced mini-ace features that extend beyond the architec- ture of the ace/mini-ace (plus). these include the enhanced bc mode; rt global circular buffer (including buffer size); the rt/mt interrupt status queue, including valid/invalid message filtering; enabling a software-assigned rt address; clock fre- quency selection; a base address for the "non-data" portion of enhanced mini-ace memory; lsb filtering for the synchronize (with data) time tag operations; and enabling a watchdog timer for the enhanced bc message sequence control engine. bc condition code register is used to enable the host proces- sor to read the current value of the enhanced bc message sequence control engine's condition flags. bc general purpose flag register allows the host processor to be able to set, clear, or toggle any of the enhanced bc message sequence control engine's general purpose condition flags. bit test status register is used to provide read-only access to the status of the protocol and ram built-in self-tests (bit). bc general purpose queue pointer provides a means for ini- tializing the pointer for the general purpose queue, for the enhanced bc mode. in addition, this register enables the host to determine the current location of the general purpose queue pointer, which is incremented internally by the enhanced bc message sequence control engine. rt/mt interrupt status queue pointer register provides a means for initializing the pointer for the interrupt status queue, for rt, mt, and rt/mt modes. in addition, this register enables the host to determine the current location of the interrupt status queue pointer, which is incremented by the rt/mt message processor. masking of status word bits, enable retries and interrupts, and specify mil-std-1553a or -1553b error handling. in rt mode, this register allows host access to the current or most recent subaddress control word. the subaddress control word is used to select the memory management scheme and enable interrupts for the current message. time tag register maintains the value of a real-time clock. the resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 s/lsb. the start-of-message (som) and end- of-message (eom) sequences in bc, rt, and message monitor modes cause a write of the current value of the time tag register to the stack area of the ram. interrupt status register #1 and #2 allow the host processor to determine the cause of an interrupt request by means of one or two read accesses. the interrupt events of the two interrupt status registers are mapped to correspond to the respective bit positions in the two interrupt mask registers. interrupt status register #2 contains an interrupt chain bit, used to indi- cate an interrupt event from interrupt status register #1. configuration registers #3, #4, and #5 are used to enable many of the enhanced mini-ace's advanced features that were implemented by the prior generation products, the ace and mini- ace (plus). for bc, rt, and mt modes, use of the enhanced mode enables the various read-only bits in configuration register #1. for bc mode, enhanced mode features include the expanded bc control word and bc block status word, addi- tional stop-on-error and stop-on-status set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, expanded status word masking, and the capability to generate interrupts following the completion of any selected message. for rt mode, the enhanced mode features include the expanded rt block status word, combined rt/selective message monitor mode, automatic setting of the terminal flag status word bit following a loop test failure; the double buffering scheme for individual receive (broadcast) subaddress- es, and the alternate (fully software programmable) rt status word. for mt mode, use of the enhanced mode enables the selective message monitor, the combined rt/selective monitor modes, and the monitor triggering capability. rt/monitor data stack address register provides a read/writable indication of the last data word stored for rt or monitor modes. bc frame time remaining register provides a read-only indication of the time remaining in the current bc frame. in the enhanced bc mode, this timer may be used for minor or major frame control, or as a watchdog timer for the bc message sequence control processor. the resolution of this register is 100 s/lsb. bc time remaining to next message register provides a read-only indication of the time remaining before the start of the next message in a bc frame. in the enhanced bc mode, this timer may also be used for the bc message sequence control processor's delay (dly) instruction, or for minor or major frame control. the resolution of this register is 1 s/lsb.
16 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c bus controller (bc) architecture the bc functionality for the enhanced mini-ace includes two separate architectures: (1) the older, non-enhanced mode, which provides complete compatibility with the previous ace and mini-ace (plus) generation products; and (2) the newer, enhanced bc mode. the enhanced bc mode offers several new powerful architectural features. these includes the incorporation of a highly autonomous bc message sequence control engine, which greatly serves to offload the operation of the host cpu. the enhanced bc's message sequence control engine provides a high degree of flexibility for implementing major and minor frame scheduling; capabilities for inserting asynchronous mes- sages in the middle of a frame; to separate 1553 message data from control/status data for the purpose of implementing double buffering and performing bulk data transfers; for implementing message retry schemes, including the capability for automatic bus channel switchover for failed messages; and for reporting various conditions to the host processor by means of 4 user- defined interrupts and a general purpose queue. in both the non-enhanced and enhanced bc modes, the enhanced mini-ace bc implements all mil-std-1553b mes- sage formats. message format is programmable on a message- by-message basis by means of the bc control word and the t/r bit of the command word for the respective message. the bc control word allows 1553 message format, 1553a/b type rt, bus channel, self-test, and status word masking to be specified on an individual message basis. in addition, automatic retries and/or interrupt requests may be enabled or disabled for individ- ual messages. the bc performs all error checking required by mil-std-1553b. this includes validation of response time, sync type and sync encoding, manchester ii encoding, parity, bit count, word count, status word rt address field, and various rt-to-rt transfer errors. the enhanced mini-ace bc response timeout value is programmable with choices of 18, 22, 50, and 130 s. the longer response timeout values allow for operation over long buses and/or the use of repeaters. in its non-enhanced mode, the enhanced mini-ace may be pro- grammed to process bc frames of up to 512 messages with no processor intervention. in the enhanced bc mode, there is no explicit limit to the number of messages that may be processed in a frame. in both modes, it is possible to program for either sin- gle frame or frame auto-repeat operation. in the auto-repeat mode, the frame repetition rate may be controlled either inter- nally, using a programmable bc frame timer, or from an external trigger input. enhanced bc mode: message sequence control one of the major new architectural features of the enhanced mini-ace series is its advanced capability for bc message sequence control. the enhanced mini-ace supports highly autonomous bc operation, which greatly offloads the operation of the host processor. the operation of the enhanced mini-ace's message sequence control engine is illustrated in figure 2. the bc message sequence control involves an instruction list pointer register; an instruction list which contains multiple 2-word entries; a message control/status stack, which contains multiple 8-word or 10-word descriptors; and data blocks for individual messages. the initial value of the instruction list pointer register is initialized by the host processor (via register 0d), and is incremented by the bc message sequence processor (host readable via register 03). during operation, the message sequence control processor fetches the operation referenced by the instruction list pointer register from the instruction list. figure 2. bc message sequence control op code data block message control/status parameter (pointer) block bc instruction list bc instruction list pointer register bc control word command word (rx command for rt-to-rt transfer) data block pointer time-to-next message time tag word block status word loopback word rt status word 2nd (tx) command word (for rt-to-rt transfer) 2nd rt status word (for rt-to-rt transfer) initialitize by register 0d (rd/wr); read current value via register 03 (rd only)
17 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c note that the pointer parameter referencing the first word of a message's control/status block (the bc control word) must con- tain an address value that is modulo 8 . also, note that if the message is an rt-to-rt transfer, the pointer parameter must contain an address value that is modulo 16 . op codes the instruction list pointer register references a pair of words in the bc instruction list: an op code word, followed by a parameter word. the format of the op code word, which is illustrated in fig- ure 3, includes a 5-bit op code field and a 5-bit condition code field. the op code identifies the instruction to be executed by the bc message sequence controller. most of the operations are conditional, with execution dependent on the contents of the condition code field. bits 3-0 of the condi- tion code field identifies a particular condition. bit 4 of the condi- tion code field identifies the logic sense ("1" or "0") of the select- ed condition code on which the conditional execution is depen- dent. table 36 lists all the op codes, along with their respective mnemonic, code value, parameter, and description. table 37 defines all the condition codes. eight of the condition codes (8 through f) are set or cleared as the result of the most recent message. the other eight are defined as "general purpose" condition codes gp0 through gp7. there are three mechanisms for programming the values of the general purpose condition code bits: (1) they may be set, cleared, or toggled by the host processor, by means of the bc general purpose flag register; (2) they may be set, cleared, or toggled by the bc message sequence control processor, by means of the gp flag bits (flg) instruction; and (3) gp0 and gp1 only (but none of the others) may be set or cleared by means of the bc message sequence control proces- sor's compare frame timer (cft) or compare message timer (cmt) instructions. the host processor also has read-only access to the bc condi- tion codes by means of the bc condition code register. note that four (4) instructions are unconditional . these are compare to frame timer (cft), compare to message timer (cmt), gp flag bits (flg), and execute and flip (xqf). for these instructions, the condition code field is "don't care". that is, these instructions are always executed, regardless of the result of the condition code test. all of the other instructions are conditional. that is, they will only be executed if the condition code specified by the condition code field in the op code word tests true. if the condition code field tests false, the instruction list pointer will skip down to the next instruction. as shown in table 36, many of the operations include a single- word parameter. for an xeq (execute message) operation, the parameter is a pointer to the start of the message ? s control / status block. for other operations, the parameter may be an address, a time value, an interrupt pattern, a mechanism to set or clear general purpose flag bits, or an immediate value. for several op codes, the parameter is "don't care" (not used). as described above, some of the op codes will cause the mes- sage sequence control processor to execute messages. in this case, the parameter references the first word of a message control/status block. with the exception of rt-to-rt transfer messages, all message status/control blocks are eight words long: a block control word, time-to-next-message parameter, data block pointer, command word, status word, loopback word, block status word, and time tag word. in the case of an rt-to-rt transfer message, the size of the message control/status block increases to 16 words. however, in this case, the last six words are not used; the ninth and tenth words are for the second command word and second status word. the third word in the message control/status block is a pointer that references the first word of the message's data word block. note that the data word block stores only data words, which are to be either transmitted or received by the bc. by segregating data words from command words, status words, and other con- trol and "housekeeping" functions, this architecture enables the use of convenient, usable data structures, such as circular buffers and double buffers. other operations support program flow control; i.e., jump and call capability. the call capability includes maintenance of a call stack which supports a maximum of four (4) entries; there is also a return instruction. in the case of a call stack overrun or under- run, the bc will issue a call stack pointer register error interrupt, if enabled. other op codes may be used to delay for a specified time; start a new bc frame; wait for an external trigger to start a new frame; do comparisons based on frame time and time-to-next message; load the time tag or frame time registers; halt; and issue host interrupts. in the case of host interrupts, the message control processor passes a 4-bit user-defined interrupt vector to the host, by means of the enhanced mini-ace's interrupt status register. the purpose of the flg instruction is to enable the message sequence controller to set, clear, or toggle the value(s) of any or all of the eight general purpose condition flags. the op code parity bit encompasses all sixteen bits of the op code word. this bit must be programmed for odd parity. if the message sequence control processor fetches an undefined op code word, an op code word with even parity, or bits 9-5 of an op figure 3. bc op code format 15 10 11 12 13 14 5 6 7 8 9 0 1 2 3 4 1 0 0 opcode field 1 1 0 condition code field
18 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c code word do not have a binary pattern of 01010, the message sequence control processor will immediately halt the bc's oper- ation. in addition, if enabled, a bc trap op code interrupt will be issued. also, if enabled, a parity error will result in an op code parity error interrupt. table 37 describes the condition codes. table 36. bc operations for message sequence control instruction mnemonic op code (hex) parameter conditional or unconditional description interrupt request execute message irq xeq 0006 0001 interrupt bit pattern in 4 ls bits message control / status block address conditional conditional generate an interrupt if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. the passed parameter (interrupt bit pattern) specifies which of the enhanced bc irq bit(s) (bits 5-2) will be set in interrupt status register #2. only the four lsbs of the passed parameter are used. a parameter where the four lsbs are logic "0" will not generate an interrupt. executes the message at the specified message control/status block address if the condition flag tests true, otherwise con- tinue execution at the next opcode in the instruction list. compare to frame timer halt jump cft hlt jmp 000a 0007 0002 delay time value (resolution = 100s / lsb) not used (don ? t care) instruction list address unconditional conditional conditional compare time value to frame time counter. the lt/gp0 and eq/gp1 flag bits are set or cleared based on the results of the compare. if the value of the cft's parameter is less than the value of the frame time counter, then the lt/gp0 and ne/gp1 flags will be set, while the gt-eq/gp0 and eq/gp1 flags will be cleared. if the value of the cft's parameter is equal to the value of the frame time counter, then the gt-eq/gp0 and eq/gp1 flags will be set, while the lt/gp0 and ne/gp1 flags will be cleared. if the value of the cft's parameter is greater than the current value of the frame time counter, then the gt- eq/gp0 and ne/gp1 flags will be set, while the lt/gp0 and eq/gp1 flags will be cleared. stop execution of the message sequence control program until a new bc start is issued by the host if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. jump to the opcode specified in the instruction list if the con- dition flag tests true, otherwise continue execution at the next opcode in the instruction list. compare to message timer delay subroutine call cmt dly cal 000b 0008 0003 delay time value (resolution = 1s / lsb) delay time value (resolution = 1s) instruction list address unconditional conditional conditional compare time value to message time counter. the lt/gp0 and eq/gp1 flag bits are set or cleared based on the results of the compare. if the value of the cmt's parameter is less than the value of the message time counter, then the lt/gp0 and ne/gp1 flags will be set, while the gt-eq/gp0 and eq/gp1 flags will be cleared. if the value of the cmt's parameter is equal to the value of the mes- sage time counter, then the gt-eq/gp0 and eq/gp1 flags will be set, while the lt/gp0 and ne/gp1 flags will be cleared. if the value of the cmt's parameter is greater than the current value of the message time counter, then the gt-eq/gp0 and ne/gp1 flags will be set, while the lt/gp0 and eq/gp1 flags will be cleared. delay the time specified by the time parameter before execut- ing the next opcode if the condition flag tests true, otherwise continue execution at the next opcode without delay. the delay generated will use the time to next message timer. jump to the opcode specified by the instruction list address and push the address of the next opcode on the call stack if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. note that the maximum depth of the subroutine call stack is four . wait until frame timer = 0 subroutine return wft rtn 0009 0004 not used (don ? t care) not used (don ? t care) conditional conditional wait until frame time counter is equal to zero before continu- ing execution of the message sequence control program if the condition flag tests true, otherwise continue execution at the next opcode without delay. return to the opcode popped off the call stack if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list.
19 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c push block status word pbs 0011 not used (don't care) conditional push the block status word for the most recent message on the general purpose queue if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. table 36. bc operations for message sequence control (cont.) instruction mnemonic op code (hex) parameter description load time tag counter lt t 000d time value. resolution (s/lsb) is defined by bits 9, 8, and 7 of configuration register #2. conditional load time tag counter with time value if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. load frame timerload frame lft 000e time value (res- olution = 100 s/lsb) conditional load frame timer register with the time value parameter if the condition flag tests true, otherwise continue execu- tion at the next opcode in the instruction list. start frame timer sft 000f not used (don't care) conditional start frame time counter with time value in time frame register if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. push time tag register ppt 0010 not used (don't care) conditional push the value of the time tag register on the general purpose queue if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. push immediate value psi 0012 immediate value conditional push immediate data on the general purpose queue if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. push indirect psm 0013 memory address conditional push the data stored at the specified memory location on the general purpose queue if the condition flag tests true, otherwise continue execution at the next opcode in the instruction list. wait for external trigger wtg 0014 not used (don't care) conditional wait for a logic "0"-to-logic "1" transition on the ext_trig input signal before proceeding to the next opcode in the instruction list if the condition flag tests true, otherwise continue execution at the next opcode without delay. execute and flip xqf 0015 message control / status block address unconditional execute (unconditionally) the message referenced by the message control/status block address. following the pro- cessing of this message, if the condition flag tests true, the bc will toggle bit 4 in the message control/status block address, and store the new message block address as the updated value of the parameter following the xqf instruc- tion code. as a result, the next time that this line in the instruction list is executed, the message control/status block at the updated address ( old address xor 0010h ), rather than the old address, will be processed. if the condi- tion flag tests false, the value of the message control/status block address parameter will not change. conditional or unconditional gp flag bits flg 000c used to set, clear, or toggle gp (general purpose) flag bits (see descrip- tion) unconditional used to set, toggle, or clear any or all of the eight general purpose flags. the table below illustrates the use of the gp flag bits instruction for the case of gp0 (general purpose flag 0). bits 1 and 9 of the parameter byte affect flag gp1, bits 2 and 10 effect gp2, etc., according to the following rules: bit 8 0 0 1 0 1 0 1 1 bit 0 effect on gp0 no change set flag clear flag toggle flag
20 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c 8 table 37. bc condition codes bit code lt/gp0 eq/gp1 retry0 retry1 retry0 retry01 d e gp2 gp3 gp4 gp5 gp6 gp7 noresp gd blk xfer name (bit 4 = 0) these two bits reflect the retry status of the most recent message. the number of times that the mes- sage was retried is delineated by these two bits as shown below: retry count 1 retry count 0 number of (bit 14) (bit 13) message retries 0 0 0 0 1 1 1 0 n/a 1 1 2 functional description inverse (bit 4 = 1) gt-eq/ gp 0 ne/gp1 0 always less than or gp0 flag. this bit is set or cleared based on the results of the compare. if the value of the cmt's parameter is less than the value of the message time counter, then the lt/gp0 and ne/gp1 flags will be set, while the gt-eq/gp0 and eq/gp1 flags will be cleared. if the value of the cmt's parameter is equal to the value of the message time counter, then the gt-eq/gp0 and eq/gp1 flags will be set, while the lt/gp0 and ne/gp1 flags will be cleared. if the value of the cmt's parameter is greater than the current value of the message time counter, then the gt-eq/gp0 and ne/gp1 flags will be set , while the lt/gp0 and eq/gp1 flags will be cleared. also, general purpose flag 1 may be also be set or cleared by a flg operation. never f gp2 gp3 gp4 gp5 gp6 gp7 1 resp equal flag. this bit is set or cleared after cft or cmt operation. if the value of the cmt's parameter is equal to the value of the message time counter, then the eq/gp1 flag will be set and the ne/gp1 bit will be cleared. if the value of the cmt's parameter is not equal to the value of the message time counter, then the ne/gp1 flag will be set and the eq/gp1bit will be cleared. also, general purpose flag 1 may be also be set or cleared by a flg operation. gd blk xfer bad message good message the always bit should be set to designate an instruction as unconditional. the inverse (never) bit can be used to implement a nop instruction. c bad message indicates either a format error, loop test fail, or no response error for the most recent message. note that a "status set" condition has no effect on the "bad message/good message" condition code. fmt err fmt err 9 fmt err indicates that the received portion of the most recent message contained one or more viola- tions of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the rt's status word received from a responding rt contained an incorrect rt address field. masked status bit masked status bit b general purpose flags may be set, cleared, or toggled by a flg operation. the host processor can set, clear, or toggle these flags in the same way as the flg instruction by means of the bc general purpose flag register. indicates that one or both of the following conditions have occurred for the most recent message: (1) if one (or more) of the status mask bits (14 through 9) in the bc control word is logic "0" and the corre- sponding bit(s) is (are) set (logic "1") in the received rt status word. in the case of the reserved bits mask (bit 9) set to logic "0," any or all of the 3 reserved status word bits being set will result in a masked status set condition; and/or (2) if broadcast mask enabled/xor (bit 11 of configuration register #4) is logic "1" and the mask broadcast bit of the message's bc control word is logic "0" and the broadcast command received bit in the received rt status word is logic "1.". 2 3 4 5 6 7 noresp indicates that an rt has either not responded or has responded later than the bc no response timeout time. the enhanced mini-ace's no response timeout time is defined per mil-std-1553b as the time from the mid-bit crossing of the parity bit of the last word transmitted by the bc to the mid-sync crossing of the rt status word. the value of the no response timeout value is programmable from among the nominal values 18.5, 22.5, 50.5, and 130 s (1 s) by means of bits 10 and 9 of configuration register #5. a for the most recent message, gd blk xfer will be set to logic "1" following completion of a valid (error-free) rt-to-bc transfer, rt-to-rt transfer, or transmit mode code with data message. this bit is set to logic "0" following an invalid message. good data block transfer is always logic "0" fol- lowing a bc-to-rt transfer, a mode code with data, or a mode code without data. the loop test has no effect on good data block transfer. good data block transfer may be used to determine if the transmitting portion of an rt-to-rt transfer was error free.
21 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c bc message sequence control the bc enhanced mini-ace bc message sequence control capability enables a high degree of offloading of the host proces- sor. this includes using the various timing functions to enable autonomous structuring of major and minor frames. in addition, by implementing conditional jumps and subroutine calls, the message sequence control processor greatly simplifies the insertion of asynchronous, or "out-of-band" messages. execute and flip operation. the enhanced mini-ace bc's xqf, or "execute and flip" operation, provides some unique capabilities. following execution of this unconditional instruction, if the condition code tests true, the bc will modify the value of the current xqf instruction's pointer parameter by toggling bit 4 of the pointer. that is, if the selected condition flag tests true, the value of the parameter will be updated to the value = old address xor 0010h . as a result, the next time that this line in the instruction list is executed, the message control/status block at the updated address (old address xor 0010h) will be processed, rather than the one at the old address. the operation of the xqf instruction is illustrated in figure 4. there are multiple ways of utilizing the "execute and flip" instruc- tion. one is to facilitate the implementation of a double buffering data scheme for individual messages. this allows the message sequence control processor to "ping-pong" between a pair of data buffers for a particular message. by doing so, the host processor can access one of the two data word blocks, while the bc reads or writes the alternate data word block. a second application of the "execute and flip" capability is in con- junction with message retries. this allows the bc to not only switch buses when retrying a failed message, but to automati- cally switch buses permanently for all future times that the same message is to be processed. this not only provides a high degree of autonomy from the host cpu, but saves bc band- width, by eliminating the need for future attempts to process messages on an rt's failed channel. xqf pointer xx00h (part of) bc instruction list message control/status block 0 data block 0 xx00h message control/status block 1 data block 1 pointer pointer figure 4. execute and flip (xqf) operation
22 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c general purpose queue. the enhanced mini-ace bc allows for the creation of a general purpose queue. this data structure provides a means for the message sequence processor to con- vey information to the bc host. the bc op code repertoire pro- vides mechanisms to push various items on this queue. these include the contents of the time tag register, the block status word for the most recent message, an immediate data value, or the contents of a specified memory address. figure 5 illustrates the operation of the bc general purpose queue. note that the bc general purpose queue pointer register will always point to the next address location (modulo 64); that is, the location following the last location written by the bc message sequence control engine. if enabled, a bc general purpose queue rollover interrupt will be issued when the value of the queue pointer address rolls over at a 64-word boundary. the rollover will always occur at a modulo 64 address. last location bc general purpose queue (64 locations) bc general purpose queue pointer register next location figure 5. bc general purpose queue
23 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c remote terminal (rt) architecture the enhanced mini-ace's rt architecture builds upon that of the ace and mini-ace. the enhanced mini-ace provides multipro- tocol support, with full compliance to all of the commonly used data bus standards, including mil-std-1553a, mil-std-1553b notice 2, stanag 3838, general dynamics 16pp303, and mcaira3818, a5232, and a5690. for the enhanced mini-ace rt mode, there is programmable flexibility enabling the rt to be con- figured to fulfill any set of system requirements. this includes the capability to meet the mil-std-1553a response time require- ment of 2 to 5 s, and multiple options for mode code subad- dresses, mode codes, rt status word, and rt bit word. the enhanced mini-ace rt protocol design implements all of the mil-std-1553b message formats and dual redundant mode codes. the design has passed validation testing for mil-std- 1553b compliance. the enhanced mini-ace rt performs com- prehensive error checking including word and format validation, and checks for various rt-to-rt transfer errors. one of the main features of the enhanced mini-ace rt is its choice of memory management options. these include single buffering by subad- dress, double buffering for individual receive subaddresses, cir- cular buffering by individual subaddresses, and global circular buffering for multiple (or all) subaddresses. other features of the enhanced mini-ace rt include a set of interrupt conditions, a flexible status queue with filtering based on valid and/or invalid messages, flexible command illegalization, programmable busy by subaddress, multiple options on time tag- ging, and an "auto-boot" feature which allows the rt to initialize as an online rt with the busy bit set following power turn-on. rt memory organization table 38 illustrates a typical memory map for an enhanced mini- ace rt with 4k ram. the two stack pointers reside in fixed locations in the shared ram address space: address 0100 (hex) for the area a stack pointer and address 0104 for the area b stack pointer. in addition to the stack pointer, there are several other areas of the shared ram address space that are designat- ed as fixed locations (all shown in bold ). these are for the area a and area b lookup tables, the illegalization lookup table, the busy lookup table, and the mode code data tables. the rt lookup tables (reference table 39) provide a mecha- nism for allocating data blocks for individual transmit, receive, or broadcast subaddresses. the rt lookup tables include subad- dress control words as well as the individual data block pointers. if command illegalization is used, address range 0300-03ff is used for command illegalizing. the descriptor stack ram area, as well as the individual data blocks, may be located in any of the non-fixed areas in the shared ram address space. note that in table 38, there is no area allocated for "stack b". this is shown for purpose of simplicity of illustration. also, note that in table 38, the allocated area for the rt command stack is 256 words. however, larger stack sizes are possible. that is, the rt command stack size may be programmed for 256 words (64 messages), 512, 1024, or 2048 words (512 messages) by means of bits 14 and 13 of configuration register 3. data block 100 0fe0-0fff ? ? ? ? ? ? data block 6 0420-043f data block 5 0400-041f command illegalizing table 0300-03ff reserved data block 1-4 0280-02ff data block 0 0260-027f (not used) 0248-025f busy bit lookup table 0240-0247 lookup table b 01c0-023f lookup table a 0140-01bf mode code data 0110-013f mode code selective interrupt table 0108-010f global circular buffer b pointer stack pointer b 0105 0104 reserved 0102-0103 global circular buffer a pointer stack pointer a 0101 0100 stack a 0000-00ff description address (hex) 0106-0107 table 38. typical rt memory map (shown for 4k ram) subaddress control word lookup table (optional) sacw sa0 . . . sacw sa31 0220 . . . 023f 01a0 . . . 01bf broadcast lookup pointer ta b l e (optional) bcst sa0 . . . bcst sa31 0200 . . . 021f 0180 . . . 019f transmit lookup pointer ta b l e tx sa0 . . . tx sa31 01e0 . . . 01ff 0160 . . . 017f receive (/broadcast) lookup pointer ta b l e rx(/bcst) sa0 . . . rx(/bcst) sa31 01c0 . . . 01df 0140 . . . 015f comment description area b area a table 39. rt look-up tables
24 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c rt memory management the enhanced mini-ace provides a variety of rt memory man- agement capabilities. as with the ace and mini-ace, the choice of memory management scheme is fully programmable on a transmit/receive/broadcast subaddress basis. in compliance with mil-std-1553b notice 2, received data from broadcast messages may be optionally separated from non- broadcast received data. for each transmit, receive or broadcast subaddress, either a single-message data block, a double buffered configuration (two alternating data word blocks), or a variable-sized (128 to 8192 words) subaddress circular buffer may be allocated for data storage. the memory management scheme for individual subaddresses is designated by means of the subaddress control word (reference table 40). for received data, there is also a global circular buffer mode. in this configuration, the data words received from multiple (or all) subaddresses are stored in a common circular buffer structure. like the subaddress circular buffer, the size of the global circular buffer is programmable, with a range of 128 to 8192 data words. the double buffering feature provides a means for the host processor to easily access the most recent, complete received block of valid data words for any given subaddress. in addition to helping ensure data sample consistency, the circular buffer options provide a means for greatly reducing host processor overhead for multi-message bulk data transfer applications. end-of-message interrupts may be enabled either globally (fol- lowing all messages), following error messages, on a transmit/receive/broadcast subaddress or mode code basis, or when a circular buffer reaches its midpoint (50% boundary) or lower (100%) boundary. a pair of interrupt status registers allow the host processor to determine the cause of all interrupts by means of a single read operation. subaddress - specific circular buffer of specified size. 8192-word 1 (for receive and / or broadcast subaddresses only) global circular buffer: the buffer size is specified by configuration register #6, bits 11-9. the pointer to the global circular buffer is stored at address 0101 (for area a) or address 0105 (for area b) 1 1 1 1 0 1 1 4096-word 0 1 0 1 1024-word 0 0 0 1 512-word 1 1 0 0 256-word 0 1 0 0 128-word 1 0 0 0 f or receiv e or broadcast: double buffered f or t r ansmit: single message single message 0 0 0 0 1 0 0 0 subaddress control word bits mm0 memory management subaddress buffer scheme description mm1 double-buffered or global circular buffer (bit 15) mm2 table 40. rt subaddress control word - memory management options 2048-word 1 0 0 1
25 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c single buffered mode the operation of the single buffered rt mode is illustrated in figure 6. in the single buffered mode, the respective lookup table entry must be written by the host processor. received data words are written to, or transmitted data words are read from the data word block with starting address referenced by the lookup table pointer. in the single buffered mode, the current lookup table pointer is not updated by the enhanced mini-ace memory management logic. therefore, if a subsequent message is received for the same subaddress, the same data word block will be overwritten or overread. subaddress double buffering mode the enhanced mini-ace provides a double buffering mechanism for received data, that may be selected on an individual subad- dress basis for any or all receive (and/or broadcast) subad- dresses. this is illustrated in figure 7. it should be noted that the subaddress double buffering mode is applicable for receive data only, not for transmit data. double buffering of transmit messages may be easily implemented by software techniques. the purpose of the subaddress double buffering mode is to pro- vide data sample consistency to the host processor. this is accomplished by allocating two 32-word data word blocks for each individual receive (and/or broadcast receive) subaddress. at any given time, one of the blocks will be designated as the "active "1553 block while the other will be considered as "inac- tive". the data words for the next receive command to that sub- address will be stored in the active block. following receipt of a valid message, the enhanced mini-ace will automatically switch the active and inactive blocks for that subaddress. as a result, the latest, valid, complete data block is always accessible to the host processor. circular buffer mode the operation of the enhanced mini-ace's circular buffer rt memory management mode is illustrated in figure 8. as in the single buffered and double buffered modes, the individual lookup table entries are initially loaded by the host processor. at the start of each message, the lookup table entry is stored in the third position of the respective message block descriptor in the descriptor stack area of ram. receive or transmit data words are transferred to (from) the circular buffer, starting at the loca- tion referenced by the lookup table pointer. in general, the location after the last data word written or read (modulo the circular buffer size) during the message is written to the respective lookup table location during the end-of-message sequence. by so doing, data for the next message for the respec- tive transmit, receive(/broadcast), or broadcast subaddress will be accessed from the next lower contiguous block of locations in the circular buffer. for the case of a receive (or broadcast receive) message with a data word error, there is an option such that the lookup table pointer will only be updated following receipt of a valid message. that is, the pointer will not be updated following receipt of a message with an error in a data word. this allows failed mes- sages in a bulk data transfer to be retried without disrupting the circular buffer data structure, and without intervention by the rt's host processor. global circular buffer beyond the programmable choice of single buffer mode, double buffer mode, or circular buffer mode, programmable on an indi- vidual subaddress basis, the enhanced mini-ace rt architec- figure 6. rt single buffered mode data blocks data block data block block status word time tag word data block pointer received command word descriptor stacks look-up table addr look-up table (data block addr) 15 13 0 current area b/a configuration register stack pointers (see note) note: lookup table is not used for mode commands when enhanced mode codes are enabled.
26 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c figure 7. rt double buffered mode 15 13 0 block status word time tag word data block pointer received command word configuration register stack pointers descriptor stack current area b/a data blocks data block 1 data block 0 x..x 0 yyyyy x..x 1 yyyyy receive double buffer enable subaddress control word msb data block pointer look-up tables figure 8. rt circular buffered mode circular buffer rollover 15 13 0 received (transmitted) message data (next location) 128, 256 8192 words pointer to current data block pointer to next data block look-up table entry circular data buffer look-up tables look-up table address block status word time tag word data block pointer received command word configuration register stack pointers descriptor stack current area b/a 1. tx/rs/bcst_sa look-up table entry is updated following valid receive (broadcast) message or following completion of transit message notes: * 2. for the global circular buffer mode, the pointer is read from and re-written to address 0101 (for area a) or adress 0105 (for area b). ture provides an additional option, a variable sized global circu- lar buffer. the enhanced mini-ace rt allows for a mix of single buffered, double buffered, and individually circular buffered sub- addresses, along with the use of the global double buffer for any arbitrary group of receive(/broadcast) or broadcast subaddress- es. in the global circular buffer mode, the data for multiple receive subaddresses is stored in the same circular buffer data structure. the size of the global circular buffer may be programmed for 128, 256, 512, 1024, 2048, 4096, or 8192 words, by means of bits 11, 10, and 9 of configuration register #6. as shown in table 40, individual subaddresses may be mapped to the glob- al circular buffer by means of their respective subaddress control words. the pointer to the global circular buffer will be stored in location 0101 (for area a), or location 0105 (for area b). the global circular buffer option provides a highly efficient method for storing received message data. it allows for frequent- ly used subaddresses to be mapped to individual data blocks, while also providing a method for asynchronously received mes- sages to infrequently used subaddresses to be logged to a com- mon area. alternatively, the global circular buffer provides an efficient means for storing the received data words for all subad- dresses. under this method, all received data words are stored chronologically, regardless of subaddress.
27 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c rt descriptor stack the descriptor stack provides a chronology of all messages processed by the enhanced mini-ace rt. reference figures 6, 7, and 8. similar to bc mode, there is a four-word block descrip- tor in the stack for each message processed. the four entries to each block descriptor are the block status word, time tag word, the pointer to the start of the message's data block, and the 16- bit received command word. the rt block status word includes indications of whether a par- ticular message is ongoing or has been completed, what bus channel it was received on, indications of illegal commands, and flags denoting various message error conditions. for the double buffering, subaddress circular buffering, and global circular buffering modes, the data block pointer may be used for locating the data blocks for specific messages. note that for mode code commands, there is an option to store the transmitted or received data word as the third word of the descriptor, in place of the data block pointer. the time tag word provides a 16-bit indication of relative time for individual messages. the resolution of the enhanced mini- ace's time tag is programmable from among 2, 4, 8, 16, 32, or 64 s/lsb. there is also a provision for using an external clock input for the time tag (consult factory). if enabled, there is a time tag rollover interrupt, which is issued when the value of the time tag rolls over from ffff(hex) to 0. other time tag options include the capabilities to clear the time tag register following receipt of a synchronize (without data) mode command and/or to set the time tag following receipt of a synchronize (with data) mode command. for the latter, there is an added option to filter the "set" capability based on the lsb of the received data word being equal to logic "0". rt interrupts the enhanced mini-ace offers a great deal of flexibility in terms of rt interrupt processing. by means of the enhanced mini- ace's two interrupt mask registers, the rt may be programmed to issue interrupt requests for the following events/conditions: end-of-(every)message, message error, selected (transmit or receive) subaddress, 100% circular buffer rollover, 50% circular buffer rollover, 100% descriptor stack rollover, 50% descriptor stack rollover, selected mode code, transmitter timeout, illegal command, and interrupt status queue rollover. interrupts for 50% rollovers of stacks and circular buffers. the enhanced mini-ace rt and monitor are capable of issuing host interrupts when a subaddress circular buffer pointer or stack pointer crosses its mid-point boundary. for rt circular buffers, this is applicable for both transmit and receive subaddresses. reference figure 9. there are four interrupt mask and inter- rupt status register bits associated with the 50% rollover function: (1) rt circular buffer; (2) rt command (descriptor) stack; (3) monitor command (descriptor) stack; and (4) monitor data stack. the 50% rollover interrupt is beneficial for performing bulk data transfers. for example, when using circular buffering for a partic- ular receive subaddress, the 50% rollover interrupt will inform the host processor when the circular buffer is half full. at that time, the host may proceed to read the received data words in the upper half of the buffer, while the enhanced mini-ace rt writes received data words to the lower half of the circular buffer. later, when the rt issues a 100% circular buffer rollover interrupt, the host can proceed to read the received data from the lower half of the buffer, while the enhanced mini-ace rt continues to write received data words to the upper half of the buffer. interrupt status queue. the enhanced mini-ace rt, monitor, and combined rt/monitor modes include the capability for gen- erating an interrupt status queue. as illustrated in figure 10, this provides a chronological history of interrupt generating events and conditions. in addition to the interrupt mask register, the interrupt status queue provides additional filtering capability, such that only valid messages and/or only invalid messages may result in the creation of an entry to the interrupt status queue. queue entries for invalid and/or valid messages may be disabled by means of bits 8 and 7 of configuration register #6. the interrupt status queue is 64 words deep, providing the capa- bility to store entries for up to 32 messages. these events and conditions include both message-related and non-message related events. note that the interrupt vector queue pointer register will always point to the next location (modulo 64) fol- lowing the last vector/pointer pair written by the enhanced mini- ace rt. the pointer to the interrupt status queue is stored in the interrupt vector queue pointer register (register address 1f). this register must be initialized by the host, and is subsequently incremented by the rt message processor. the interrupt status queue is 64 words deep, providing the capability to store entries for up to 32 messages. the queue rolls over at addresses of modulo 64. the events that result in queue entries include both message-related and non- message-related events. note that the interrupt vector queue pointer register will always point to the next location (modulo 64) following the last vector/pointer pair written by the enhanced mini-ace rt, monitor, or rt/monitor. each event that causes an interrupt results in a two-word entry to be written to the queue. the first word of the entry is the inter- rupt vector. the vector indicates which interrupt event(s)/condi- tion(s) caused the interrupt. the interrupt events are classified into two categories: message interrupt events and non-message interrupt events. message- based interrupt events include end-of-message, selected mode code, format error, subaddress control word interrupt, rt circular buffer rollover, handshake failure, rt command stack rollover, transmitter timeout, mt data stack rollover, mt command stack rollover, rt command stack 50% rollover, mt data stack 50% rollover, mt command stack 50% rollover, and rt circular buffer 50% rollover. non-message interrupt
28 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c figure 10. rt (and monitor) interrupt status queue (shown for message interrupt event) interrupt vector data w o r d block descriptor stack parameter (pointer) interrupt status queue (64 locations) interrupt vector queue pointer register (if) block status word time tag data block pointer recieved command next vector figure 9. 50% and 100% rollover interrupts data pointer circular buffer* (128,256,...8192 words) look-up table recieved (transmitted) message data block status word time tag word data block pointer recieved command word descriptor stack 50% rollover interrupt 50% the example shown is for an rt subaddress circular buffer. the 50% and 100% rollover interrupts are also applicable to the rt global circulat buffer, rt command stack, monitor command stack, and monitor data stack. note 100% rollover interrupt 100%
29 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c rt command illegalization the enhanced mini-ace provides an internal mechanism for rt command word illegalizing. by means of a 256-word area in shared ram, the host processor may designate that any mes- sage be illegalized, based on the command word t/r bit, sub- address, and word count/mode code fields. the enhanced mini- ace illegalization scheme provides the maximum in flexibility, allowing any subset of the 4096 possible combinations of broad- cast/own address, t/r bit, subaddress, and word count/mode code to be illegalized. the address map of the enhanced mini-ace's illegalizing table is illustrated in table 41. table 41. illegalization table memory map 3fc 3be 37d 3c2 381 33f 300 address own addr / tx, sa 30. wc15-0 own addr / rx, sa 31. mc15-0 brdcst / tx, sa 30. wc31-16 own addr / tx, sa 1. wc15-0 own addr / rx, sa 0. mc31-16 brdcst / rx, sa 31. mc31-16 brdcst / rx, sa 0. mc15-0 description 3fd 3bf 37e 3c3 382 340 301 own addr / tx, sa 30. wc31-16 own addr / rx, sa 31. mc31-16 brdcst / tx, sa 31. mc15-0 own addr / tx, sa 1. wc31-16 own addr / rx, sa 1. wc15-0 brdcst / tx, sa 0. mc15-0 brdcst / rx,sa 0. mc31-16 3fe 3c0 37f 383 341 302 own addr / tx, sa 31. mc15-0 own addr / tx, sa 0. mc15-0 brdcst / tx, sa 31. mc31-16 own addr / rx, sa 1. wc31-16 brdcst / tx, sa 1.mc31-16 brdcst / rx, sa 1. wc15-0 ? ? ? ? ? ? ? ? ? ? ? ? 3ff 3c1 380 342 303 ? ? ? ? ? ? ? ? ? ? ? ? own addr / tx, sa 31. mc31-16 own addr / tx, sa 0. mc31-16 own addr / rx, sa 0. mc15-0 brdcst / tx, sa 1. wc15-0 brdcst / rx, sa 1. wc31-16 events/conditions include time tag rollover, rt address parity error, ram parity error, and bit completed. bit 0 of the interrupt vector (interrupt status) word indicates whether the entry is for a message interrupt event (if bit 0 is logic "1") or a non-message interrupt event (if bit 0 is logic "0"). it is not possible for one entry on the queue to indicate both a message interrupt and a non-message interrupt. as illustrated in figure 10, for a message interrupt event, the parameter word is a pointer. the pointer will reference the first word of the rt or mt command stack descriptor (i.e., the block status word). for a ram parity error non-message interrupt, the parameter will be the ram address where the parity check failed. for the rt address parity error, protocol self-test complete, and time tag rollover non-message interrupts, the parameter is not used; it will have a value of 0000. if enabled, an interrupt status queue rollover inter- rupt will be issued when the value of the queue pointer address rolls over at a 64-word address boundary.
30 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c monitor architecture the enhanced mini-ace includes three monitor modes: (1) a word monitor mode. (2) a selective message monitor mode. (3) a combined rt/message monitor mode. for new applications, it is recommended that the selective mes- sage monitor mode be used, rather than the word monitor mode. besides providing monitor filtering based on rt address, t/r bit, and subaddress, the message monitor eliminates the need to determine the start and end of messages by software. word monitor mode in the word monitor terminal mode, the enhanced mini-ace monitors both 1553 buses. after the software initialization and monitor start sequences, the enhanced mini-ace stores all command, status, and data words received from both buses. for each word received from either bus, a pair of words is stored to the enhanced mini-ace's shared ram. the first word is the word received from the 1553 bus. the second word is the monitor identification (id), or "tag" word. the id word contains information relating to bus channel, word validity, and inter-word time gaps. the data and id words are stored in a circular buffer in the shared ram address space. word monitor memory map a typical word monitor memory map is illustrated in table 43. table 43 assumes a 64k address space for the enhanced mini- ace's monitor. the active area stack pointer provides the address where the first monitored word is stored. in the example, it is assumed that the active area stack pointer for area a (loca- tion 0100) is initialized to 0000. the first received data word is stored in location 0000, the id word for the first word is stored in location 0001, etc. busy bit the enhanced mini-ace rt provides two different methods for setting the busy status word bit: (1) globally, by means of configuration register #1; or (2) on a t/r-bit/subaddress basis, by means of a ram lookup table. if the host cpu asserts the b usy bit to logic ? 0 ? in configuration register #1, the enhanced mini-ace rt will respond to all non-broadcast commands with the busy bit set in its rt status word. alternatively, there is a busy lookup table in the enhanced mini- ace shared ram. by means of this table, it is possible for the host processor to set the busy bit for any selectable subset of the 128 combinations of broadcast/own address, t/r bit, and sub- address. if the busy bit is set for a transmit command, the enhanced mini- ace rt will respond with the busy bit set in the status word, but will not transmit any data words. if the busy bit is set for a receive command, the rt will also respond with the busy status bit set. there are two programmable options regarding the reception of data words for a non-mode code receive command for which the rt is busy: (1) to transfer the received data words to shared ram; or (2) to not transfer the data words to shared ram. rt address the enhanced mini-ace offers several different options for des- ignating the remote terminal address. these include the follow- ing: (1) hardwired, by means of the 5 rt address inputs, and the rt address parity input; (2) by means of the rt address (and parity) inputs, but latched via hardware, on the rising edge of the rt_ad_lat input signal; (3) input by means of the rt address (and parity) inputs, but latched via host software; and (4) software programmable, by means of an internal register. in all four configurations, the rt address is readable by the host processor. rt built-in-test (bit) word the bit map for the enhanced mini-ace's internal rt built-in- test (bit) word is indicated in table 42. rt auto-boot option if utilized, the rt pin-programmable auto-boot option allows the enhanced mini-ace rt to automatically initialize as an active remote terminal with the busy status word bit set to logic "1" immediately following power turn-on. this is a useful feature for mil-std-1760 applications, in which the rt is required to be responding within 150 ms after power-up. this feature is avail- able for versions of the enhanced mini-ace with 4k words of ram. other rt features the enhanced mini-ace includes options for the terminal flag status word bit to be set either under software control and/or automatically following a failure of the loopback self-test. other software programmable rt options include software program- mable rt status and rt bit words, automatic clearing of the service request bit following receipt of a transmit vector word mode command, options regarding data word transfers for the busy and message error (illegal) status word bits, and options for the handling of 1553a and reserved mode codes. command word contents error 0(lsb) rt-to-rt 2nd command word error 1 rt-to-rt no response error 2 transmitter shutdown b rt-to-rt gap / sync address error 3 parity / manchester error received 4 incorrect sync received 5 low word count 6 high word count 7 bit test failure 8 terminal flag inhibited 9 transmitter shutdown a 10 handshake failure 12 loop test failure a 13 loop test failure b 14 transmitter timeout 15(msb) description bit 11 table 42. rt bit word
31 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c the current monitor address is maintained by means of a counter register. this value may be read by the cpu by means of the data stack address register. it is important to note that when the counter reaches the stack pointer address of 0100 or 0104, the initial pointer value stored in this shared ram location will be overwritten by the monitored data and id words. when the internal counter reaches an address of ffff (or 0fff, for an enhanced mini-ace with 4k ram), the counter rolls over to 0000. word monitor trigger in the word monitor mode, there is a pattern recognition trigger and a pattern recognition interrupt. the 16-bit compare word for both the trigger and the interrupt is stored in the monitor trigger word register. the pattern recognition interrupt is enabled by setting the mt pattern trigger bit in interrupt mask register #1. the pattern recognition trigger is enabled by setting the trigger enable bit in configuration register #1 and selecting either the start-on-trigger or the stop-on-trigger bit in configuration register #1. the word monitor may also be started by means of a low-to-high transition on the ext_trig input signal. selective message monitor mode the enhanced mini-ace selective message monitor provides monitoring of 1553 messages with filtering based on rt address, t/r bit, and subaddress with no host processor inter- vention. by autonomously distinguishing between 1553 com- mand and status words, the message monitor determines when messages begin and end, and stores the messages into ram, based on a programmable filter of rt address, t/r bit, and sub- address. third received 1553 word ? ? received 1553 words and identification word ? ? ? ? ? ffff stack pointer (fixed location - gets overwritten) 0100 ? ? ? ? ? ? third identification word 005 second identification word 0003 second received 1553 word 0002 first identification word 0001 first received 1553 word 0000 function hex address 0004 table 43. typical word monitor memory map the selective monitor may be configured as just a monitor, or as a combined rt/monitor. in the combined rt/monitor mode, the enhanced mini-ace functions as an rt for one rt address (including broadcast messages), and as a selective message mon- itor for the other 30 rt addresses. the enhanced mini-ace message monitor contains two stacks, a command stack and a data stack, that are independent from the rt command stack. the pointers for these stacks are located at fixed locations in ram. monitor selection function following receipt of a valid command word in selective monitor mode, the enhanced mini-ace will reference the selective mon- itor lookup table to determine if the particular command is enabled. the address for this location in the table is determined by means of an offset based on the rt address, t/r bit, and subaddress bit 4 of the current command word, and concate- nating it to the monitor lookup table base address of 0280 (hex). the bit location within this word is determined by subaddress bits 3-0 of the current command word. if the specified bit in the lookup table is logic "0", the command is not enabled, and the enhanced mini-ace will ignore this com- mand. if this bit is logic "1", the command is enabled and the enhanced mini-ace will create an entry in the monitor command descriptor stack (based on the monitor command stack pointer), and store the data and status words associated with the com- mand into sequential locations in the monitor data stack. in addi- tion, for an rt-to-rt transfer in which the receive command is selected, the second command word (the transmit command) is stored in the monitor data stack. the address definition for the selective monitor lookup table is illustrated in table 44. subaddress 4 0(lsb) transmit / receive 1 rtad_0 2 logic ? 0 ? rtad_1 3 rtad_2 4 rtad_3 5 rtad_4 6 logic ? 1 ? 7 logic ? 0 ? 8 logic ? 1 ? 9 logic ? 0 ? 10 logic ? 0 ? 12 logic ? 0 ? 13 logic ? 0 ? 14 logic ? 0 ? 15(msb) description bit 11 table 44. monitor selection table lookup address
32 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c miscellaneous clock input the enhanced mini-ace decoder is capable of operating from a 10, 12, 16, or 20 mhz clock input. depending on the configura- tion of the specific model enhanced mini-ace terminal, the selection of the clock input frequency may be chosen by one of either two methods. for all versions, the clock frequency may be specified by means of the host processor writing to configuration register #6. with the second method, which is applicable only for the versions incorporating 4k (but not 64k) words of internal ram, the clock frequency may be specified by means of the input signals that are otherwise used as the a15 and a14 address lines. encoder/decoders for the selected clock frequency, there is internal logic to derive the necessary clocks for the manchester encoder and decoders. for all clock frequencies, the decoders sample the receiver out- puts on both edges of the input clock. by in effect doubling the decoders' sampling frequency, this serves to widen the tolerance to zero-crossing distortion, and reduce the bit error rate. for interfacing to fiber optic transceivers (e.g., for mil-std-1773 applications), the decoders are capable of operating with single- ended, rather than double-ended, input signals. for applications involving the use of single-ended transceivers, it is suggested that you contact the factory at ddc regarding a transceiverless version of the enhanced mini-ace. selective message monitor memory organization a typical memory map for the ace in the selective message monitor mode, assuming a 4k ram space, is illustrated in table 45. this mode of operation defines several fixed locations in the ram. these locations are allocated in a way in which none of them overlap with the fixed rt locations. this allows for the combined rt/selective message monitor mode. the fixed memory map consists of two monitor command stack pointers (locations 102 and 106 hex), two monitor data stack pointers (locations 103 and 107 hex), and a selective message monitor lookup table (locations 0280 through 02ff hex). for this example, the monitor command stack size is assumed to be 1k words, and the monitor data stack size is assumed to be 2k words. figure 11 illustrates the selective message monitor operation. upon receipt of a valid command word, the enhanced mini-ace will reference the selective monitor lookup table to determine if the current command is enabled. if the current command is dis- abled, the enhanced mini-ace monitor will ignore (and not store) the current message. if the command is enabled, the monitor will create an entry in the monitor command stack at the address location referenced by the monitor command stack pointer, and an entry in the monitor data stack starting at the location refer- enced by the monitor data stack pointer. the format of the information in the data stack depends on the format of the message that was processed. for example, for a bc-to-rt transfer (receive command), the monitor will store the command word in the monitor command descriptor stack, with the data words and the receiving rt's status word stored in the monitor data stack. the size of the monitor command stack is programmable, with choices of 256, 1k, 4k, or 16k words. the monitor data stack size is programmable with choices of 512, 1k, 2k, 4k, 8k, 16k, 32k or 64k words. monitor command stack pointer b (fixed location) monitor data stack a 0800-0fff monitor command stack a 0400-07ff not used 0300-03ff selective monitor lookup table (fixed location) 0280-02ff not used 0108-027f monitor data stack pointer b (fixed location) 0107 not used 0104-0105 monitor data stack pointer a (fixed location) 0103 monitor command stack pointer a (fixed location) 0102 not used 0000-0101 description address (hex) 0106 table 45. typical selective message monitor memory map (shown for 4k ram for ? monitor only ? mode) monitor interrupts. selective monitor interrupts may be issued for end-of-message and for conditions relating to the monitor command stack pointer and monitor data stack pointer. the lat- ter, which are shown in figure 9, include command stack 50% rollover, command stack 100% rollover, data stack 50% rollover, and data stack 100% rollover. the 50% rollover interrupts may be used to inform the host processor when the command stack or data stack is half full. at that time, the host may proceed to read the received messages in the upper half of the respective stack, while the enhanced mini-ace monitor writes messages to the lower half of the stack. later, when the monitor issues a 100% stack rollover interrupt, the host can proceed to read the received data from the lower half of the stack, while the enhanced mini-ace monitor contin- ues to write received data words to the upper half of the stack. interrupt status queue like the enhanced mini-ace rt, the selective monitor mode includes the capability for generating an interrupt status queue. as illustrated in figure 10, this provides a chronological histo- ry of interrupt generating events. besides the two interrupt mask registers, the interrupt status queue provides additional filter- ing capability, such that only valid messages and/or only invalid messages may result in entries to the interrupt status queue. the interrupt status queue is 64 words deep, providing the capa- bility to store entries for up to 32 monitored messages.
33 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c 15 13 0 block status word time tag word data block pointer received command word configuration register #1 monitor command stack pointers monitor command stacks current area b/a monitor data stacks monitor data block #n + 1 monitor data block #n current command word monitor data stack pointers if this bit is "0" (not selected) no words are stored in either the command stack or data stack. in addition, the command and data stack pointers will not be updated. note selective monitor lookup tables selective monitor enable (see note) offset based on rta4-rta0, t/r, sa4 figure 11. selective message monitor memory management time tag the enhanced mini-ace includes an internal read/writable time tag register. this register is a cpu read/writable 16-bit counter with a programmable resolution of either 2, 4, 8, 16, 32, or 64 s per lsb. another option allows software controlled incrementing of the time tag register. this supports self-test for the time tag register. for each message processed, the value of the time tag register is loaded into the second location of the respective descriptor stack entry ("time tag word") for both the bc and rt modes. the functionality involving the time tag register that's compati- ble with ace/mini-ace (plus) includes: the capability to issue an interrupt request and set a bit in the interrupt status register when the time tag register rolls over ffff to 0000; for rt mode, the capability to automatically clear the time tag register following reception of a synchronize (without data) mode com- mand, or to load the time tag register following a synchronize (with data) mode command. additional time tag features supported by the enhanced mini- ace include the capability for the bc to transmit the contents of the time tag register as the data word for a synchronize (with data) mode command; the capability for the rt to "filter" the data word for the synchronize with data mode command, by only loading the time tag register if the lsb of the received data word is "0"; an instruction enabling the bc message sequence control engine to load the time tag register with a specified value; and an instruction enabling the bc message sequence control engine to write the value of the time tag register to the general purpose queue. interrupts the enhanced mini-ace series terminals provide many pro- grammable options for interrupt generation and handling. the interrupt output pin (int ) has three software programmable modes of operation: a pulse , a level output cleared under soft- ware control, or a level output automatically cleared following a read of the interrupt status register (#1 or #2). individual interrupts are enabled by the two interrupt mask registers. the host processor may determine the cause of the interrupt by reading the two interrupt status registers, which provide the current state of interrupt events and conditions. the interrupt status registers may be updated in two ways. in one interrupt handling mode, a particular bit in interrupt status register #1 or #2 will be updated only if the event occurs and the corresponding bit in interrupt mask register #1 or #2 is enabled. in the enhanced interrupt handling mode, a particular bit in one of the interrupt status registers will be updated if the event/con- dition occurs regardless of the value of the corresponding interrupt mask register bit. in either case, the respective interrupt mask register (#1 or #2) bit is used to enable an inter- rupt for a particular event/condition. the enhanced mini-ace supports all the interrupt events from ace/mini-ace (plus), including ram parity error, transmitter timeout, bc/rt command stack rollover, mt command stack
34 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c and data stack rollover, handshake error, bc retry, rt address parity error, time tag rollover, rt circular buffer rollover, bc message, rt subaddress, bc end-of-frame, format error, bc status set, rt mode code, mt trigger, and end-of-message. for the enhanced mini-ace's enhanced bc mode, there are four user-defined interrupt bits. the bc message sequence control engine includes an instruction enabling it to issue these interrupts at any time. for rt and monitor modes, the enhanced mini-ace architecture includes an interrupt status queue. this provides a mechanism for logging messages that result in interrupt requests. entries to the interrupt status queue may be filtered such that only valid and/or invalid messages will result in entries on the queue. the enhanced mini-ace incorporates additional interrupt condi- tions beyond ace/mini-ace (plus), based on the addition of interrupt mask register #2 and interrupt status register #2. this is accomplished by chaining the two interrupt status registers using the interrupt chain bit (bit 0) in interrupt status register #2 to indicate that an interrupt has occurred in interrupt status register #1. additional interrupts include "self-test completed", masking bits for the enhanced bc control interrupts, 50% rollover interrupts for rt command stack, rt circular buffers, mt command stack, and mt data stack; bc op code parity error, (rt) illegal command, (bc) general purpose queue or (rt/mt) interrupt status queue rollover, call stack pointer register error, bc trap op code, and the four user-defined interrupts for the enhanced bc mode. built-in test a salient feature of the enhanced mini-ace is its highly autonomous self-test capability. this includes both protocol and ram self-tests. either or both of these self-tests may be initiated by command(s) from the host processor. the protocol test consists of a comprehensive toggle test of the terminal's logic. the test includes testing of all registers, manchester decoders, protocol logic, and memory management logs. this test is completed in approximately 32,000 clock cycles. that is, about 1.6 ms with a 20 mhz clock, 2.0 ms at 16 mhz, 2.7 ms at 12 mhz, and 3.2 ms at 10 mhz. there is also a separate built-in test for the enhanced mini- ace's 4k x 16 or 64k x 16 shared ram. this test consists of writing and then reading/verifying the two walking patterns "data = address" and "data = address inverted". this test takes 10 clock cycles per word. for an enhanced mini-ace with 4k words of ram, this is about 2.0 ms with a 20 mhz clock, 2.6 ms at 16 mhz, 3.4 ms at 12 mhz, or 4.1 ms at 10 mhz. for an enhanced mini-ace with 64k words of ram, this test takes about 32.8 ms with a 20 mhz clock, 40.1 ms at 16 mhz, 54.6 ms at 12 mhz, or 65.6 ms at 10 mhz. the enhanced mini-ace built-in protocol test is performed auto- matically at power-up. in addition, the protocol or ram self-tests may be initiated by a command from the host processor, via the start/rest register. for rt mode, this may include the host processor invoking self-test following receipt of an initiate self-test mode command. the results of the self-test are host accessible by means of the bit status register. for rt mode, the result of the self-test may be communicated to the bus controller via bit 8 of the rt bit word ("0" = pass, "1" = fail). assuming that the protocol self-test passes, all of the register and shared ram locations will be restored to their state prior to the self-test, with the exception of the 60 ram address locations 0342-037d and the time tag register. note that for rt mode, these locations map to the illegalization lookup table for "broadcast transmit subaddresses 1 through 30" (non-mode code subaddresses). since mil-std-1553 does not define these as valid command words, this section of the illegalization lookup table is normally not used during rt operation. the time tag register will continue to increment during the self-test. if there is a failure of the protocol self-test, it is possible to access information about the first failed vector. this may be done by means of the enhanced mini-ace's upper registers (register addresses 32 through 63). through these registers, it is possible to determine the self-test rom address of the first failed vector, the expected response data pattern (from the rom), the register or memory address, and the actual (incorrect) data value read from register or memory. the on-chip self-test rom is 4k x 24. note that the ram self-test is destructive. that is, following the ram self-test, regardless of whether the test passes or fails, the shared ram is not restored to its state prior to this test. following a failed ram self-test, the host may read the internal ram to determine which location(s) failed the walking pattern test. ram parity the bc/rt/mt version of the enhanced mini-ace is available with options of 4k or 64k words of internal ram. for the 64k option, the ram is 17 bits wide. the 64k x 17 internal ram allows for parity generation for ram write accesses, and parity checking for ram read accesses. this includes host ram accesses, as well as accesses by the enhanced mini-ace ? s inter- nal logic. when the enhanced mini-ace detects a ram parity error, it reports it to the host processor by means of an interrupt and a register bit. also, for the rt and selective message monitor modes, the ram address where a parity error was detected will be stored on the interrupt status queue (if enabled). relocatable memory management locations in the enhanced mini-ace's default configuration, there is a fixed area of shared ram addresses, 0000h-03ff, that is allocated for storage of the bc's or rt's pointers, counters, tables, and other "non-message" data structures. as a means of reducing the overall memory address space for using multiple enhanced mini- aces in a given system (e.g., for use with the dma interface configuration), the enhanced mini-ace allows this area of ram to be relocated by means of 6 configuration register bits. to pro- vide backwards compatibility to ace and mini-ace, the default for this ram area is 0000h-03ffh. host processor interface the enhanced mini-ace supports a wide variety of processor interface configurations. these include shared ram and dma configurations, straightforward interfacing for 16-bit and 8-bit buses, support for both non-multiplexed and multiplexed
35 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c host enhanced 55 ? 55 ? ch. a tx/rxa tx/rxa 55 ? 55 ? ch. b tx/rxb tx/rxb rtad4-rtad0 rt address, parity rtadp d15-d0 +5v (3.3v) (note 5) clk in clock oscillator n/c n/c polarity_sel (note 2) zero_wait (note 3) address decoder select mem/reg rd/wr strbd readyd tag_clk rd/wr cpu strobe cpu acknowledge (note 4) reset +5v mstclr ssflag/ext_trig int cpu interrupt request notes: 3. zero_wait should be strapped to logic "1" for non-zero wait interface and to logic "0" for zero wait interface. 4. cpu acknowledge processor input only for non-zero wait type of interface. 5. +3.3v power for bu-61743 / 61843 / 61864 only 1. cpu address latch signal provided by processors with multiplexed address/data buses. for processors with non-multiplexed address and data busses, addr_lat should be connected to +5v. 2. if polarity_sel = "1", rd/wr is high to read, low to write. if polarity_sel = "0", rd/wr is low to read, high to write. a15-a12 a11-a0 n/c addr_lat transparent/buffered cpu address latch (note 1) +5v 16/8_bit trigger_sel msb/lsb +5v mini-ace figure 12. host processor interface - 16-bit buffered configuration address/data buses, non-zero wait mode for interfacing to a processor address/data buses, and zero wait mode for interfac- ing (for example) to microcontroller i/o ports. in addition, with respect to the ace/mini-ace, the enhanced mini-ace provides two major improvements: (1) reduced maximum host access time for shared ram mode; and (2) increased maximum dma grant time for the transparent/dma mode. the enhanced mini-ace's maximum host holdoff time (time prior to the assertion of the read yd handshake signal) has been sig- nificantly reduced. for ace/mini-ace, this maximum holdoff time is 17 internal word transfer cycles, resulting in an overall holdoff time of approximately 4.6 s, using a 16 mhz clock. by comparison, using the enhanced mini-ace's enhanced cpu access feature, this worst-case holdoff time is reduced signifi- cantly, to a single internal transfer cycle. for example, when operating the enhanced mini-ace in its 16-bit buffered, non-zero wait configuration with a 16 mhz clock input, this results in a maximum overall host transfer cycle time of 632 ns for a read cycle, or 570 ns for a write cycle. in addition, for using the ace or mini-ace in the transparent/dma configuration, the maximum request-to-grant time, which occurs prior to an rt start-of-message sequence, is 4.0 s with a 16 mhz clock, or 3.5 s with a 12 mhz clock. for the enhanced mini-ace functioning as a mil-std-1553b rt, this time has been increased to 8.5 s at 10 mhz, 10 s at 16 mhz, 9 s at 12 mhz, and 10.5 s at 20mhz. this provides greater flexibility, particularly for systems in which a host has to arbitrate among multiple dma requestors. by far, the most commonly used processor interface configura- tion is the 16-bit buffered, non-zero wait mode. this configuration may be used to interface between 16-bit or 32-bit microproces- sors and an enhanced mini-ace. in this mode, only the enhanced mini-ace's internal 4k or 64k words of internal ram are used for storing 1553 message data and associated "house- keeping" functions. that is, in this configuration, the enhanced mini-ace will never attempt to access memory on the host bus. figure 12 illustrates a generic connection diagram between a 16-bit (or 32-bit) microprocessor and an enhanced mini-ace for the 16-bit buffered configuration, while figures 13 and 14, and associated tables illustrate the processor read and write timing respectively.
36 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c clock in valid t7 t3 t8 t11 t13 t15 valid t10 t4 t9 t12 t19 valid t16 t17 select (note 2,7) (note 2) (note 3,4,7) (note 4,5) strbd mem/reg rd/wr ioen (note 2,6) (note 6) (note 6) (note 7,8,9) readyd a15-a0 d15-d0 t5 t1 t2 t6 t14 t18 figure 13. cpu reading ram / register (16-bit buffered, nonzero wait) notes: 1. for the 16-bit buffered nonzero wait configuration, transparent/b uffered must be connected to logic "0". zer o_w ait and dtreq / 16/8 must be connected to logic "1". the inputs trigger_sel and msb/lsb may be connected to either +5v or ground. 2. select and strbd may be tied together. ioen goes low on the first rising clk edge when select strbd is sampled low (satisfying t1) and the enhanced mini-ace's protocol/memory management logic is not accessing the internal ram. when this occurs, ioen goes low, start- ing the transfer cycle. after ioen goes low, select may be released high. 3. mem/reg must be presented high for memory access, low for register access. 4. mem/reg and rd/wr are buffered transparently until the first falling edge of clk after ioen goes low. after this clk edge, mem/reg and rd/wr become latched internally. 5. the logic sense for rd/wr in the diagram assumes that polarity_sel is connected to logic "1." if polarity_sel is connected to logic "0," rd/wr must be asserted low to read. 6. the timing for ioen , read yd and d15-d0 assumes a 50 pf load. for loading above 50 pf, the validity of ioen , read yd , and d15-d0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. the timing for a15-a0, mem/reg and select assumes that addr-lat is connected to logic "1." refer to address latch timing for additional details. 8. the address bus a15-a0 is internally buffered transparently until the first rising edge of clk after ioen goes low. after this clk edge, a15-a0 become latched internally. 9. setup time given for use in worst case timing calculations. none of the enhanced mini-ace input signals are required to be syn chronized to the system clock. when select and strbd do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an addi- tional clock cycle will be inserted between the falling clock edge that latches mem/reg and rd/wr and the rising clock edge that latches the address (a15-a0). when this occurs, the delay from ioen falling to read yd falling (t11) increases by one clock cycle and the address hold time (t10) must be increased be one clock cycle.
37 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 3, 4, 5, 7 3, 4, 5, 7 6 6 6 6 2 2, 6 7, 8 6, 9 6, 9 6, 9 3, 4, 5, 7 6 6 6, 9 7, 8, 9 3, 4, 5, 7 6 3, 4, 5, 7 3, 4, 5, 7 2, 6 2, 6 max typ min units max typ min description ref 4.4 155 555 655 138 430 2.8 3.7 35 27 62 45 61 44 40 0 40 0 40 40 0 25 355 35 165 150 135 265 250 235 205 187.5 170 30 23 11 315 300 285 30 15 40 12 16 10 2.2 105 15 notes 2, 9 2, 6 117 s 7.2 (contended access, with enhanced cpu select = ? 0 ? @ 10 mhz) ns 150 (uncontended access @ 10 mhz) ns 550 (contended access, with enhanced cpu select = ? 1 ? @ 12 mhz) ns 650 (contended access, with enhanced cpu select = ? 1 ? @ 10 mhz) ns 133 (uncontended access @ 12 mhz) ns 425 (contended access, with enhanced cpu select = ? 1 ? s @ 16 mhz) s 4.6 (contended access, with enhanced cpu select = ? 0 ? @ 16 mhz) s 6.0 (contended access, with enhanced cpu select = ? 0 ? @ 12 mhz) ns 40 @ 10 mhz t3 t4 ns 32 @ 12 mhz ns 67 @ 10 mhz ns 50 @ 12 mhz ns 71 @ 10 mhz ns 54 @ 12 mhz ns 40 clock in rising edge delay to output data valid t19 ns 0 strbd high hold time from read yd rising t18 ns 40 strbd rising delay to output data tri-state t17 ns 0 output data hold time following strbd rising edge t16 ns 30 strbd rising edge delay to ioen rising edge and read yd rising edge t15 ns read yd falling to strbd rising release time t14 ns 40 clock in rising edge delay to read yd falling t13 t12 ns 0 select hold time following ioen falling t6 ns 30 @ 16 mhz ns 350 (contended access, with enhanced cpu select = ? 1 ? @ 20 mhz) ns 30 address valid setup time prior to clock in rising edge t9 ns 165 150 135 ioen falling delay to read yd falling (@ 20 mhz) ns 265 250 235 @ 12 mhz ns 205 187.5 170 @ 16 mhz ns 30 mem/reg , rd/wr hold time following clock in falling edge t8 ns 33 @ 16 mhz ns 21 output data valid prior to read yd falling (@ 20 mhz) ns 315 300 285 @ 10 mhz ns 30 address hold time following clock in rising edge t10 t11 ns 10 mem/reg , rd/wr setup time prior to clock in falling edge t7 ns 40 clock in rising edge delay to ioen falling edge t5 ns 17 time for address to become valid following select and strbd low (@ 20 mhz) ns 21 @ 16 mhz ns 15 time for mem/reg and rd/wr to become valid following select and strbd low(@ 20 mhz) s 3.6 (contended access, with enhanced cpu select = ? 0 ? @ 20 mhz) ns 100 select and strbd low to ioen low (uncontended access @ 20 mhz) t2 ns 10 select and strbd low setup time prior to clock rising edge t1 3.3v logic 5v logic table for figure 13. cpu reading ram or registers (shown for 16-bit, buffered, nonzero wait mode) ns 112 (uncontended access @ 16 mhz)
38 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c clock in t1 t6 t7 t2 t3 t18 t16 valid t8 t9 t14 t15 t17 valid t12 t10 t4 t11 t5 valid t13 select (note 2,7) (note 2) (note 3,4,7) (note 4,5) strbd mem/reg rd/wr ioen (note 2,6) (note 6) (note 9,10) (note 7,8,9,10) readyd a15-a0 d15-d0 figure 14. cpu writing ram / register (16-bit buffered, nonzero wait) notes: 1. for the 16-bit buffered nonzero wait configuration transparent/b uffered must be connected to logic "0", zer o_w ait and dtreg / 16/8 must be connected to logic "1". the inputs trigger_sel and msb/lsb may be connected to either +5v or ground. 2. select and strbd may be tied together. ioen goes low on the first rising clk edge when select strbd is sampled low (satisfying t1) and the enhanced mini-ace's protocol/memory management logic is not accessing the internal ram. when this occurs, ioen goes low, start- ing the transfer cycle. after ioen goes low, select may be released high. 3. mem/reg must be presented high for memory access, low for register access. 4. mem/reg and rd/wr are buffered transparently until the first falling edge of clk after ioen goes low. after this clk edge, mem/reg and rd/wr become latched internally. 5. the logic sense for rd/wr in the diagram assumes that polarity_sel is connected to logic "1." if polarity_sel is connected to logic "0," rd/wr must be asserted high to write. 6. the timing for the ioen and read yd outputs assumes a 50 pf load. for loading above 50 pf, the validity of ioen and read yd is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. the timing for a15-a0, mem/reg , and select assumes that addr-lat is connected to logic "1." refer to address latch timing for additional details. 9. the address bus a15-a0 and data bus d15-d0 are internally buffered transparently until the first rising edge of clk after ioe n goes low. after this clk edge, a15-a0 and d15-d0 become latched internally. 10 setup time given for use in worst case timing calculations. none of the enhanced mini-ace input signals are required to be syn chronized to the system clock. when select and strbd do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an additional clock cycle may be inserted between the falling clock edge that latches mem/reg and rd/wr and the rising clock edge that latches the address (a15-a0) and data (d15-d0). when this occurs, the delay from ioen falling to read yd falling (t14) increases by one clock cycle and the address and data hold time (t12 and t13) must be increased by one clock.
39 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c (uncontended access @ 16 mhz) 112 ns table for figure 14. cpu writing ram or registers (shown for 16-bit, buffered, nonzero wait mode) 3.3v logic 5v logic @ 16 mhz t1 select and strbd low setup time prior to clock rising edge 10 ns 50 t2 select and strbd low to ioen low (uncontended access @ 20 mhz) 100 ns ns (contended access, with enhanced cpu select = ? 0 ? @ 20 mhz) 3.6 s time for mem/reg and rd/wr to become valid following select and strbd low(@ 20 mhz) 15 ns @ 16 mhz 21 ns 45 time for address to become valid following select and strbd low (@ 20 mhz) 17 ns time for data to become valid following select and strbd low ( @ 20 mhz ) 37 ns t7 select hold time following ioen falling 0 ns @ 12 mhz t10 address valid setup time prior to clock in rising edge 30 ns ioen falling delay to read yd falling @ 20 mhz 85 100 115 ns t12 address valid hold time prior to clock in rising edge 30 ns 70 85 100 115 6, 9 @ 16 mhz ns t8 mem/reg , rd/wr setup time prior to clock in falling edge 10 ns 110 125 140 ns 110 125 140 6, 9 @ 12 mhz 152 167 65 t11 data valid setup time prior to clock in rising edge 10 ns t9 mem/reg , rd/wr setup time following clock in falling edge 30 ns t5 (contended access, with enhanced cpu select = ? 1 ? @ 20 mhz) 350 ns @ 10 mhz @ 16 mhz 30 ns t6 clock in rising edge delay to ioen falling edge 40 ns 87 t13 data valid hold time following clock in rising edge 10 ns ns t15 clock in rising edge delay to read yd falling 40 ns t16 read yd falling to strbd rising release time ns 82 t17 strbd rising delay to ioen rising edge and read yd rising edge 30 ns t18 strbd high hold time from read yd rising 10 ns 182 ns 152 167 182 6, 9 t14 @ 10 mhz 185 200 215 ns 185 200 215 6, 9 @ 12 mhz 50 ns t4 @ 10 mhz 67 ns @ 12 mhz 32 ns t3 @ 10 mhz 40 ns (contended access, with enhanced cpu select = ? 0 ? @ 12 mhz) 6.0 s (contended access, with enhanced cpu select = ? 0 ? @ 16 mhz) 4.6 s (contended access, with enhanced cpu select = ? 1 ? @ 16 mhz) 425 ns (uncontended access @ 12 mhz) 133 ns (contended access, with enhanced cpu select = ? 1 ? @ 10 mhz) 650 ns (contended access, with enhanced cpu select = ? 1 ? @ 12 mhz) 550 ns (uncontended access @ 10 mhz) 150 ns (contended access, with enhanced cpu select = ? 0 ? @ 10 mhz) 7.2 s 117 2, 6 2, 10 notes 15 105 2.2 10 16 12 32 0 35 30 15 15 35 355 25 40 15 40 40 10 45 62 27 35 3.7 2.8 430 138 655 555 155 4.4 ref description min typ max units min typ max 2, 6 2, 6 3, 4, 5, 7 3, 4, 5, 7 2 7, 8 7, 8, 9 3, 4, 5, 7 3, 4, 5, 7 2, 6 6 9 6 6 3, 4, 5, 7 3, 4, 5, 7 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6
40 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c interface to mil-std-1553 bus figure 15 illustrates the interface between the various versions of the enhanced mini-ace series and a mil-std-1553 bus. connections for both direct (short stub) and transformer (long stub) coupling, as well as the nominal peak-to-peak voltage lev- els at various points (when transmitting), are indicated in the dia- gram. figure 15. enhanced mini-ace interface to mil-std-1553 bus enhanced mini-ace data bus z 0 55 ? 55 ? tx/rx tx/rx (1:2.5) 11.6 vpp 28 vpp 1 ft max z 0 (1:1.79) 11.6 vpp 20 vpp (1:1.14) coupling transformer 0.75 z 0 0.75 z 0 long stub (transformer coupled) 20 ft max 28 vpp short stub (direct coupled) or note: z 0 = 70 to 85 ohms isolation transformer isolation transformer 7 vpp 7 vpp enhanced mini-ace
41 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c transformers in selecting isolation transformers to be used with the enhanced mini-ace, there is a limitation on the maximum amount of leak- age inductance. if this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by mil-std-1553. in addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. the maximum allowable leakage inductance is 6.0 h, and is measured as follows: the side of the transformer that connects to the enhanced mini-ace is defined as the ? primary ? winding. if one side of the primary is shorted to the primary center-tap, the inductance should be measured across the ? secondary ? (stub side) winding. this inductance must be less than 6.0 h. similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured across the ? secondary ? (stub side) wind- ing must also be less than 6.0 h. the difference between these two measurements is the ? differential ? leakage inductance. this value must be less than 1.0 h. beta transformer technology corporation (bttc), a subsidiary of ddc, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct cou- pled, and 1:1.79 transformer coupled. table 46 provides a list- ing of many of these transformers. for further information, contact bttc at 631-244-7393 or at www.bttc-beta.com. dlp-7014 slp-8007 slp-8024 not recommended lpb-5015 b-3310 hlp-6015 dual epoxy transformer, side by side, surface mount, 0.930" x 0.630", 0.155" max height dlp-7115 (see note 3) dual epoxy transformer, side by side, surface mount, 1.410" x 0.750", 0.130" max height single metal transformer, hermetically sealed, surface mount, 0.630" x 0.630", 0.175" max height b-3261 hlp-6014 dual epoxy transformer, side by side, flat pack, 0.930" x 0.630", 0.155" max height single metal transformer, hermetically sealed, flat pack, 0.630" x 0.630", 0.175" max height b-3300 dual epoxy transformer, side by side, through-hole, 0.930" x 0.630", 0.155" max height tst-9027 dual epoxy transformer, twin stacked, flat pack, 0.625" x 0.625", 0.280" max height tst-9017 dual epoxy transformer, twin stacked, surface mount, 0.625" x 0.625", 0.280" max height tst-9007 dual epoxy transformer, twin stacked, 0.625" x 0.625", 0.280" max height b-3819 lpb-5014 single epoxy transformer, surface mount, hi-temp solder, 0.625" x 0.625", 0.220" max height. may be used with bu-6xxxxx4 versions of the enhanced mini-ace.b-3819 single epoxy transformer, flat pack, 0.625" x 0.625", 0.150" max height b-3227 single epoxy transformer, surface mount, 0.625" x 0.625", 0.275" max height b-3231 single epoxy transformer, flat pack, 0.625" x 0.625", 0.275" max height b-3818 b-3067 b-3226 single epoxy transformer, through-hole, 0.625" x 0.625", 0.220" max height. may be used with bu-6xxxxx4 versions of the enhanced mini-ace. single epoxy transformer, through-hole, 0.625" x 0.625", 0.250" max height bttc part no. transformer configuration single epoxy transformer, surface mount, 0.625" x 0.625", 0.150" max height b-3229 single epoxy transformer, through hole, transformer coupled only, 0.500" x 0.350", 0.250" max height table 46. bttc transformers for use with enhanced mini-ace notes: 1. for the bu-6xxxxx4 versions of the enhanced mini-ace, which include the mcair-compatible transceivers, only the b-3818 or b-3 819 transformers (shown in bold in the table) may be used. 2. for the bu-6xxxxx3 versions of the enhanced mini-ace with -1553b transceivers, any of the transformers listed in the table ma y be used. 3. dlp-7115 operates to +105 c max. all other transformers listed operate to +130 c max.
42 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c +5v vcc ch a 72 channel a transceiver power. tx/rx-a (i/o) 5 analog transmit/receive input/outputs. connect directly to 1553 isolation transformers. tx/rx-a (i/o) 7 tx/rx-b (i/o) 13 tx/rx-b (i/o) 16 +5v vcc ch b 20 channel b transceiver power. +5v / +3.3v logic 37 logic power. for bu-61864/61843/61743, this pin must be connected to +3.3v . for bu-61865/61845/61745, this pin must be connected to +5v . ground 17, 18, 19, 65, 67 ground. +5v ram 26 (bu-6186xfx/gx only) for bu-61864fx/gx, bu-61865fx/gx, and bu-61860bx this pin must be connected to +5v. note: for bu-6184xfx/gx and bu-6174xfx/gx, this pin assumes the function upaddren. table 48. 1553 isolation transformer signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin table 47. power and ground signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin signal descriptions by functional groups
43 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c 16-bit bi-directional data bus. this bus interfaces the host processor to the enhanced mini-ace's internal registers and internal ram. in addition, in transparent mode, this bus allows data transfers to take place between the internal protocol/memory management logic and up to 64k x 16 of external ram. most of the time, the outputs for d15 through d0 are in the high impedance state. they drive outward in the buffered or transparent mode when the host cpu reads the internal ram or registers. also, in the transparent mode, d15-d0 will drive outward (towards the host) when the protocol/management logic is accessing (either reading or writing) internal ram, or writing to external ram. in the transparent mode, d15-d0 drives inward when the cpu writes internal registers or ram, or when the protocol/memory management logic reads external ram. d10 54 d9 51 d8 46 d7 47 d6 36 d5 45 d4 39 d3 44 d2 43 d1 38 d0 (lsb) 42 d15 (msb) 53 d14 50 d13 48 d12 49 d11 52 table 49. data bus signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin
44 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c a15 / clk_sel_1 a15 66 for bu-6186x (64k ram versions), this signal is always configured as address line a15 (msb). refer to the description for a11-a0 below. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "1", this signal operates as address line a15. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "0", this signal operates as clk_sel_1. in this case, a15/clk_sel_1 and a14/clk_sel_0 are used to select the enhanced mini-ace's clock frequency, as follows: cloc k clk_sel_1 clk_sel_0 f requency 0 0 10 mhz 0 1 20 mhz 1 0 12 mhz 1 1 16 mhz a14 / clk_sel_0 a14 8 for bu-6186x (64k ram versions), this signal is always configured as address line a14. refer to the description of a11-a0 below. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "1", this signal operates as a14. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "0", then this signal operates as clk_sel_1. in this case, clk_sel_1 and clk_sel_0 are used to select the enhanced mini-ace's clock frequency, as defined in the description for a15/clk_sel1 above. a13 / vcc -logic 71 for bu-6186x (64k ram versions), this signal is always configured as address line a13. refer to the description for a11-a0 below. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "1", this signal operates as a13. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "0", then this signal must be connected to +5v/+3.3v-logic (logic "1"). a13 table 50. processor address bus signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin 4k ram 64k ram
45 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c a11 a11 3 lower 12 bits of 16-bit bi-directional address bus. in both the buffered and transparent modes, the host cpu accesses the enhanced mini-ace registers and internal ram by means of a11 - a0 (4k version). for the 64k versions, a15 - a12 are also used for this purpose. in buffered mode, a12-a0 (or a15-a0) are inputs only. in the transparent mode, a12- a0 (or a15-a0) are inputs during cpu accesses and become outputs, driving outward (towards the cpu) when the 1553 protocol/memory management logic accesses up to 64k words of external ram. in transparent mode, the address bus is driven outward only when the signal dt a ck is low (indicating that the enhanced mini-ace has control of the ram interface bus) and ioen is high, indicating a non-host access. most of the time, including immediately after power turn-on, a12-a0 (or a15-a0) will be in high impedance (input) state. a10 a10 4 a9 a9 69 a8 a8 6 a7 a7 11 a6 a6 22 a5 a5 68 a4 a4 9 a3 a3 10 a2 a2 12 a1 a1 27 a0 (lsb) a0 (lsb) 15 table 50. processor address bus (cont.) signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin 4k ram 64k ram a12 / r tboo t 70 for bu-6186x (64k ram versions), this signal is always configured as address line a12. refer to the description for a11-a0 below. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "1", this signal operates as a12. for bu-6184x/6174x (4k ram versions), if upaddren is connected to logic "0", then this signal functions as r tboo t . if r tboo t is connected to logic "0", the enhanced mini-ace will initialize in rt mode with the busy status word bit set follow- ing power turn-on. if r tboo t hardwired to logic "1", the enhanced mini-ace will ini- tialize in either idle mode (for an rt-only part), or in bc mode (for a bc/rt/mt part). a12
46 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c select (i) 61 generally connected to a cpu address decoder output to select the enhanced mini-ace for a transfer to/from either ram or register. strbd (i) 62 strobe data. used in conjunction with select to initiate and control the data transfer cycle between the host processor and the enhanced mini-ace. strbd must be asserted low through the full duration of the transfer cycle. rd / wr 63 read/write. for a host processor access, rd/wr selects between reading and writing. in the 16-bit buffered mode, if pol_sel is logic "0, then rd/wr should be low (logic ? 0") for read accesses and high (logic "1") for write accesses. if pol_sel is logic "1", or the interface is configured for a mode other than 16-bit buffered mode, then rd/wr is high (logic "1") for read accesses and low (logic "0") for write access- es. addr_lat(i) / memoe (o) 14 memory output enable or address latch. in buffered mode, the addr_lat input is used to configure the buffers for a15-a0, select , mem/reg , and msb/lsb (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). that is, the enhanced mini-ace's internal transparent latches will track the values on a15-a0, select , mem/reg , and msb/lsb when addr_lat is high, and latch the values when addr_lat goes low. in general, for interfacing to processors with a non-multiplexed address/data bus, addr_lat should be hardwired to logic "1". for interfacing to processors with a multiplexed address/data bus, addr_lat should be connected to a signal that indicates a valid address when addr_lat is logic "1". in transparent mode, memoe output signal is used to enable data outputs for external ram read cycles (normally connected to the oe input signal on external ram chips). zer o w ait (i) / memwr (o) 23 memory write or zero wait . in buffered mode, input signal (zer o w ait ) used to select between the zero wait mode (zer o w ait = ? 0") and the non-zero wait mode (zer o w ait = "1"). in transparent mode, active low output signal (memwr ) asserted low during memory write transfers to strobe data into external ram (normally connected to the wr input signal on external ram chips). 16 / 8 (i) / dtreq (o) 24 data transfer request or data bus select. in buffered mode, input signal 16/8 used to select between the 16 bit data transfer mode (16/8 = "1") and the 8-bit data transfer mode (16/8 = "0"). in transparent mode (16-bit only), active low level output signal dtreq used to request access to the processor/ram interface bus (address and data buses). msb / lsb (i) / dtgr t (i) 64 data transfer grant or most significant byte/least significant byte. in 8-bit buffered mode, input signal (msb/lsb) used to indicate which byte is currently being transferred (msb or lsb). the logic sense of msb/lsb is controlled by the pol_sel input. msb/lsb is not used in the 16-bit buffered mode. in transparent mode, active low input signal (dtgr t ) asserted in response to the dtreq output to indi- cate that control of the external processor/ram bus has been transferred from the host processor to the enhanced mini-ace. table 51. processor interface control signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin
47 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c pol_sel (i) / dt a ck (o) 29 data transfer acknowledge or polarity select. in 16-bit buffered mode, if pol_sel is connected to logic "1", rd/wr should be asserted high (logic "1") for a read operation and low (logic "0") for a write opera- tion. in 16-bit buffered mode, if pol_sel is connected to logic "0", rd/wr should be asserted low (logic "0") for a read operation and high (logic "1") for a write operation. in 8-bit buffered mode (transparent/ b uffered = ? 0" and 16/8 = "0"), pol_sel input signal used to control the logic sense of the msb/lsb signal. if pol_sel is connected to logic ? 0", msb/lsb should be asserted low (logic "0") to indicate the transfer of the least significant byte and high (logic "1") to indicate the transfer of the most significant byte. if pol_sel is connected to logic ? 1", msb/lsb should be assert- ed high (logic "1") to indicate the transfer of the least significant byte and low (logic "0") to indicate the transfer of the most significant byte. in transparent mode, active low output signal (dt a ck ) used to indicate acceptance of the processor/ram interface bus in response to a data transfer grant (dtgr t ). the enhanced mini-ace's ram transfers over a15-a0 and d15-d0 will be framed by the time that dt a ck is asserted low. trig_sel (i) / memena_in (i) 28 memory enable or trigger select input. in 8-bit buffered mode, input signal (trig-sel) used to select the order in which byte pairs are transferred to or from the enhanced mini-ace by the host processor. in the 8-bit buffered mode, trig_sel should be asserted high (logic 1) if the byte order for both read operations and write operations is msb followed by lsb. trig_sel should be asserted low (logic 0) if the byte order for both read operations and write operations is lsb followed by msb. this signal has no operation in the 16-bit buffered mode (it does not need to be connected). in transparent mode, active low input memena_in , used as a chip select (cs ) input to the enhanced mini- ace's internal shared ram. if only internal ram is used, should be connected directly to the output of a gate that is or'ing the dt a ck and ioen output signals. mem / reg (i) 1 memory/register. generally connected to either a cpu address line or address decoder output. selects between memory access (mem/reg = "1") or register access (mem/reg = "0"). ssfla g (i) / ext_trig(i) 32 subsystem flag (rt) or external trigger (bc/word monitor) input. in rt mode, if this input is asserted low, the subsystem flag bit will be set in the enhanced mini-ace's rt status word. if the ssfla g input is logic "0" while bit 8 of configuration register #1 has been programmed to logic "1" (cleared), the subsystem flag rt status word bit will become logic "1," but bit 8 of configuration register #1, ssfla g , will return logic "1" when read. that is, the sense on the ssfla g input has no effect on the subsystem flag register bit. in the non-enhanced bc mode, this signal operates as an external trigger input. in bc mode, if the exter- nal bc start option is enabled (bit 7 of configuration register #1), a low to high transition on this input will issue a bc start command, starting execution of the current bc frame. in the enhanced bc mode, during the execution of a wait for external trigger (wtg) instruction, the enhanced mini-ace bc will wait for a low-to-high transition on ext_trig before proceeding to the next instruction. in the word monitor mode, if the external trigger is enabled (bit 7 of configuration register #1), a low to high transition on this input will initiate a monitor start. this input has no effect in message monitor mode. table 51. processor interface control (cont.) signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin
48 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c transparent / b uffered 55 used to select between the buffered mode (when strapped to logic ? 0 ? ) and transparent/dma mode (when strapped to logic ? 1") for the host processor interface. ioen (o) 58 i/o enable. tri-state control for external address and data buffers. generally not used in buffered mode. when low, indicates that the enhanced mini-ace is currently performing a host access to an internal reg- ister, or internal or (for transparent mode) external ram. in transparent mode, ioen (low) should be used to enable external address and data bus tri-state buffers. read yd 56 handshake output to host processor. for a nonzero wait state read access, read yd is asserted at the end of a host transfer cycle to indicate that data is available to be read on d15 through d0 when asserted (low). for a nonzero wait state write cycle, read yd is asserted at the end of the cycle to indicate that data has been transferred to a register or ram location. for both nonzero wait reads and writes, the host must assert strbd low until read yd is asserted low. in the (buffered) zero wait state mode, this output is normally logic "1", indicating that the enhanced mini-ace is in a state ready to accept a subsequent host transfer cycle. in zero wait mode, read yd will transition from high to low during (or just after) a host transfer cycle, when the enhanced mini-ace initiates its internal transfer to or from registers or internal ram. when the enhanced mini-ace completes its internal transfer, read yd returns to logic "1", indicating it is ready for the host to initiate a subsequent transfer cycle. rtad4 (msb) (i) 35 rt address inputs. if bit 5 of configuration register #6, rt address source, is programmed to logic "0" (default), then the enhanced mini-ace's rt address is provided by means of these 5 input signals. in addition, if rt address source is logic "0", the source of rt address parity is rtadp. there are many methods for using these input signals for designating the enhanced mini-ace's rt address. for details, refer to the description of rt_ad_lat. if rt address source is programmed to logic "1", then the enhanced mini-ace's source for its rt address and parity is under software control, via data lines d5-d0. in this case, the rtad4-rtad0 and rtadp signals are not used. rtad3 (i) 34 rtad2 (i) 21 rtad1 (i) 41 rtad0 (lsb) (i) 33 rt_ad_lat (i) 31 rt address latch. input signal used to control the enhanced mini-ace's internal rt address latch. if rt_ad_lat is connected to logic "0", then the enhanced mini-ace rt is configured to accept a hardwired (transparent) rt address from rtad4-rtad) and rtadp. if rt_ad_lat is initially logic "0", and then transitions to logic "1", the values presented on rtad4-rtad0 and rtadp will be latched internally on the rising edge of rt_ad_lat. if rt_ad_lat is connected to logic "1", then the enhanced mini-ace's rt address is latchable under host processor control. in this case, there are two possibilities: (1) if bit 5 of configuration register #6, rt address source, is programmed to logic "0" (default), then the source of the rt address is the rtad4-rtad0 and rtadp input signals; (2) if rt address source is programmed to logic "1", then the source of the rt address is the lower 6 bits of the processor data bus, d5-d1 (for rtad4-0) and d0 (for rtadp). in either of these two cases (with rt_ad_lat = "1"), the processor will cause the rt address to be latched by: (1) writing bit 15 of configuration register #3, enhanced mode, to logic "1"; (2) writing bit 3 of configuration register #4, latch rt address with configuration register #5, to logic "1"; and (3) writing to configuration register #5. in the case of rt address source = "1", then the values of rt address and rt address parity must be written to the lower 6 bits of configuration register #5, via d5-d0. in the case where rt address source = "0", the bit values presented on d5-d0 become "don't care" . rtadp 40 remote terminal address parity. this input signal must provide an odd parity sum with rtad4-rtad0 in order for the rt to respond to non-broadcast commands. that is, there must be an odd number of logic "1"s from among rtad-4-rtad0 and rtadp. table 51. processor interface control (cont.) signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin table 52. rt address signal name description bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx pin
49 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c upaddren (bu-6174x, bu-6184x only) for bu-61864/61865fx/gx, this pin signal is +5v-ram and must be connected to +5v. for bu-6174x and 6184x, this signal is used to control the function of the upper 4 address inputs (a15- a12). for these versions of enhanced mini-ace, if upaddren is connected to logic "1", then these four signals operate as address lines a15-a12. for bu-6184x/6174x, if upaddren is connected to logic "0", then a15 and a14 function as clk_sel_1 and clk_sel_0 respectively; a13 must be connected to vcc-logic (+5v or +3.3v); and a12 functions as r tboo t . 26 int (o) interrupt request output. if the level/pulse interrupt bit (bit 3) of configuration register #2 is logic "0", a negative pulse of approximately 500ns in width is output on int to signal an interrupt request. if level/pulse is high, a low level interrupt request output will be asserted on int . the level interrupt will be cleared (high) after either: (1) the processor writes a value of logic "1" to interrupt reset, bit 2 of the start/reset register; or (2) if bit 4 of configuration register #2, interrupt status auto- clear is logic "1", then it will only be necessary to read the interrupt status register (#1 and/or #2) that is requesting an interrupt that has been enabled by the corresponding interrupt mask register. however, for the case where both interrupt status register #1 and interrupt status register #2 have bits set reflect- ing interrupt events, it will be necessary to read both interrupt status registers in order to clear int . 57 incmd (o) / mcrst (o) in-command or mode code reset. the function of this pin is controlled by bit 0 of configuration register #7, mode code reset/incmd select. if this register bit is logic "0" (default), incmd will be active on this pin. for bc, rt, or selective message monitor modes, incmd is asserted low whenever a message is being processed by the enhanced mini- ace. in word monitor mode, incmd will be asserted low for as long as the monitor is online. for rt mode, if mode code reset/incmd select is programmed to logic "1", mcrst will be active. in this case, mcrst will be asserted low for two clock cycles following receipt of a reset remote terminal mode command. in bc or monitor modes, if mode code reset/incmd select is logic "1", this signal is inoperative; i.e., in this case, it will always output a value of logic "1". 25 table 53. miscellaneous signal name description pin bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx
50 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c (*) note that the test output pins are recessed pads located on the bottom of the package. clock_in (i) 20 mhz, 16 mhz, 12 mhz, or 10 mhz clock input. 30 xcvr_tp (zap volta) for factory test only. do not connect for normal operation. p1(*) xcvr_tp (readoutb) p2(*) xcvr_tp (readouta) p3(*) xcvr_tp (clock) p4(*) xcvr_tp (reset ) p5(*) xcvr_tp (zap voltb) p6(*) mstclr (i) master clear. negative true reset input, normally asserted low following power turn-on. when coming out of a ? reset ? condition, please note that the rise time of mstclr must be less than 10 s. 2 tx_inh_a (i) transmitter inhibit inputs for the channel a and channel b mil-std-1553 transmitters. for normal opera- tion, these inputs should be connected to logic "0". to force a shutdown of channel a and/or channel b, a value of logic "1" should be applied to the respective tx_inh input. 59 tx_inh_b (i) 60 table 53. miscellaneous (cont.) signal name description pin bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx table 54. factory test signal name description pin bu-6186xfx/gx bu-6184xfx/gx bu-6174xfx/gx
data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c d1 38 d4 rtadp qfp d1 rtad1 39 d12 bu-61864(5) bc / rt / mt (64k ram) 40 d13 d7 41 d8 package d0 42 d5 d2 43 d3 44 d5 d8 d3 d7 45 d2 46 d0 47 rtad1 d13 48 bu-61843(5) bc / rt / mt, (4k ram) bu-61743(5) rt only, (4k ram) rtadp d12 49 d4 d10 d14 50 d15 d9 51 d11 52 d15 d10 d11 53 d9 54 d14 strbd select tx_inh_b ioen 58 tx_inh_b ioen select 60 61 strbd 62 logic gnd a15/clk_sel_1 a15 66 logic gnd 67 a5 a5 68 +5v vcc-ch. a +5v vcc-ch. a 72 a13/+5v/3.3v logic int read yd transparent/ b uffered transparent/ b uffered 55 read yd 56 int 57 rd / wr tx_inh_a tx_inh_a 59 rd / wr 63 logic gnd msb/lsb/dtgr t msb/lsb/dtgr t logic gnd 64 65 a12/r tboo t a9 a9 69 a12 70 a13 71 mem/reg 1 mstclr a11 qfp mem/reg a10 2 a2 bu-61864(5) bc / rt / mt (64k ram) 3 a7 a3 4 a4 package tx/rx_a 5 a14/clk_sel_0 a8 6 rtad3 tx/rx_a 7 a14 a4 tx/rx_a a3 8 a8 9 tx/rx_a 10 a10 a7 11 table 55. flatpack and gull lead package pinouts bu-61843(5) bc / rt / mt, (4k ram) bu-61743(5) rt only, (4k ram) a11 a2 12 mstclr +5v vcc-ch. b logic gnd logic gnd logic gnd tx/rx_b 13 tx/rx-b addr_lat/memoe 14 a0 15 tx/rx-b logic gnd a0 logic gnd 16 addr_lat/memoe 17 tx/rx_b 18 logic gnd 19 +5v vcc-ch. b 20 upaddren incmd /mcrst 8 /16-bit/dtreq zer o w ait /memwr a6 rtad2 21 a6 zer o w ait /memwr rtad2 8 /16-bit/dtreq 22 23 24 incmd /mcrst 25 +5v ram 26 clock_in pol_sel/dt a ck trig_sel/memena_in a1 a1 trig_sel/memena_in 27 28 pol_sel/dt a ck 29 clock_in 30 rtad0 ssfla g / ext_trig rt_ad_lat rt_ad_lat ssfla g / ext_trig 31 32 rtad0 33 rtad3 34 +5v/3.3v logic d6 rtad4 rtad4 d6 35 36 +5v/3.3v logic 37 51 pin functions
52 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c table 56. flatpack and gull lead factory test points bu-61864(5) bc / rt / mt (64k ram) package bu-61843(5) bc / rt / mt, (4k ram) bu-61743(5) rt only, (4k ram) qfp p1 ** xcvr tp (zap volta) xcvr tp (zap volta) p2 ** xcvr tp (readoutb) xcvr tp (readoutb) p3 ** xcvr tp (readouta) xcvr tp (readouta) n/a p4 ** gnd xcvr tp(clock) gnd xcvr tp(clock) n/a p5 ** gnd xcvr tp (reset_l) gnd xcvr tp (reset_l) n/a p6 ** gnd xcvr tp (zap voltb) gnd xcvr tp (zap voltb) ** note that the test output pins on the flat pack are pads located on the bottom of the package.
53 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c 1.000 sq 0.010 (25.400 0.254) 72 1 view "b" 0.018 0.002 (0.457 0.051) 0.050 0.005 (1.270 0.127) notes: 1) dimensions are in inches (mm). 2) package material: alumina (al 2 o 3 ) 3) lead material: kovar, plated by 50 in. minimum nickel under 60 in. minimum gold. 4) there are 6 test pads located on the bottom of the package. these pads are recessed so as not to interfere when mounting the hybrid there are no user connections to these pads. view "b" 2.000 0.015 (50.800 0.381) 0.500 0.005 (12.70 0.127) 0.200 0.005 (5.080 0.127) 0.850 0.008 (21.590 0.203) 0.010 0.002 (0.254 0.051) 0.035 0.005 (0.889 0.127) 0.040 0.004 (1.016 0.102) 0.050 0.005 (1.270 0.127) 0.090 0.010 (2.286 0.254) 0.155 max (3.94) bottom view side view view "a" view "a" index denotes pin no. 1 p2 p1 p6 p5 p4 p3 0.100 dia. (2.540) (see note 4) 1.024 0.014 nom. (26.010 0.356) figure 16. mechanical outline drawing for 72-lead flatpack
54 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c 1.00 sq 0.01 (25.40 0.25) 72 1 view "b" notes: 1) dimensions are in inches (mm). 2) package material: alumina (al 2 o 3 ) 3) lead material: kovar, plated by 50 in. minimum nickel under 60 in. minimum gold. 4) there are 6 test pads located on the bottom of the package. these pads are recessed so as not to interfere when mounting the hybrid. there are no user connections to these pads. view "b" 1.38 0.02 (35.05 0.51) 0.19 0.01 (4.83 0.25) 0.850 0.008 (21.590 0.203) 0.08 min flat (2.03) 0.155 max (3.94) 0.018 0.002 (0.457 0.051) 0.050 0.005 (1.270 0.127) bottom view side view view "a" index denotes pin no. 1 p2 p1 p6 p5 p4 p3 0.100 dia. (2.540) (see note 4) 0.010 0.002 (0.254 0.051) 0.012 r. max (0.305 r.) 0.05 min flat (1.27) 1.024 0.014 nom. (26.010 0.356) view "a" 0.006 -0.004,+0.010 (0.152 -0.100,+ 0.254) 0.050 0.005 (1.27 0.127) figure 17. mechanical outline drawing for 72-pin gull lead package
55 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c ordering information bu-61745f3-120x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above test criteria: 0 = standard testing 2 = mil-std-1760 amplitude compliant (not available with voltage/transceiver option 4 ? mcair compatible ? ) process requirements: 0 = standard ddc practices, no burn-in 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in temperature range**/data requirements: 1 = -55 c to +125 c 2 = -40 c to +85 c 3 = 0 c to +70 c 4 = -55 c to +125 c with variables test data 5 = -40 c to +85 c with variables test data 6 = custom part (reserved) 7 = custom part (reserved) 8 = 0 c to +70 c with variables test data voltage/transceiver option: 3 = +5 volts rise/fall times = 100 to 300 ns (-1553b) 4 = +5 volts rise/fall times = 200 to 300 ns (-1553b and mcair compatible)(not available with test criteria option 2 ? mil-std-1760 amplitude compliant) package type: f = 72-lead flat pack g = 72-lead ? gull wing ? (formed lead) logic / ram voltage 3 = 3.3 volt (applicable only for bu-61743 and bu-61843) 4 = 3.3 and 5 volt (applicable only for bu-61864) 5 = 5 volt product type: bu-6174 = rt only with 4k x 16 ram bu-6184 = bc /rt / mt with 4k x 16 ram bu-6186 = bc /rt / mt with 64k x 17 ram * standard ddc processing with burn-in and full temperature test. see table on next page. ** temperature range applies to case temperature for flat pack and gull wing packages.
56 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c ? 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing
57 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c notes:
58 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c notes:
59 data device corporation www.ddc-web.com bu-6174x/6184x/6186x rev. c notes:
60 c-10/01-250 printed in the u.s.a. data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7234 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice.

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